From 9305dd08eb1af0be90e80b3d8a552f01e774f738 Mon Sep 17 00:00:00 2001
From: Angie <shunshou@gmail.com>
Date: Sun, 2 Apr 2017 04:34:38 -0700
Subject: [PATCH] remove functionality from clkgen pass due to compatibility
 issue with latest firrtl

---
 .../main/scala/transforms/clkgen/CreateClkConstraints.scala    | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala b/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala
index 1915bdbf..6975eb73 100644
--- a/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala
+++ b/tapeout/src/main/scala/transforms/clkgen/CreateClkConstraints.scala
@@ -24,7 +24,7 @@ class CreateClkConstraints(
   // TODO: Are annotations only valid on ports?
   
   def run(c: Circuit): Circuit = {
-
+/*
     val top = c.main
     
     // Remove everything from the circuit, unless it has a clock type
@@ -146,6 +146,7 @@ class CreateClkConstraints(
     clkSrcs.foreach { x => println(s"gen clk: $x")}
     clkModSinkToSourceMap.foreach { x => println(s"sink -> src: $x")}
     clkModSourceToSinkMap.foreach { x => println(s"src -> dependent sinks: $x")}
+*/
     c
   }
 }
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