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[Firechip] Include reset in tracerv tokens

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This commit is contained in:
David Biancolin
2020-01-20 12:00:23 -08:00
parent 3fbc074b01
commit 924f440385
2 changed files with 16 additions and 12 deletions
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9
generators/firechip/src/main/scala/TargetMixins.scala
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@@ -42,10 +42,13 @@ trait HasTraceIOImp extends LazyModuleImp {
outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) => outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) =>
if (p(InstantiateTracerVBridges)) { if (p(InstantiateTracerVBridges)) {
val b = TracerVBridge(node.bundle) val b = TracerVBridge(node.bundle)
// Used for verifying the TracerV bridge
if (p(PrintTracePort)) { if (p(PrintTracePort)) {
val traceprint = WireDefault(0.U(512.W)) withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) {
traceprint := b.io.traces.asUInt val traceprint = WireDefault(0.U(512.W))
printf(s"TRACEPORT ${idx}: %x\n", traceprint) traceprint := b.io.traces.asUInt
printf(s"TRACEPORT ${idx}: %x\n", traceprint)
}
} }
} }
}) })

19
generators/firechip/src/test/scala/ScalaTestSuite.scala
View File

@@ -106,15 +106,16 @@ abstract class FireSimTestSuite(
def diffTracelog(verilatedLog: String) { def diffTracelog(verilatedLog: String) {
behavior of "captured instruction trace" behavior of "captured instruction trace"
it should s"match the chisel printf in ${verilatedLog}" in { it should s"match the chisel printf in ${verilatedLog}" in {
def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = { def getLines(file: File): Seq[String] = Source.fromFile(file).getLines.toList
val lines = Source.fromFile(file).getLines.toList
lines.filter(_.startsWith(prefixFilter)) val printfPrefix = "TRACEPORT 0: "
.drop(dropLines) val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")).collect({
.map(_.stripPrefix(prefixFilter)) case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) })
}
val resetLength = 51 // Last bit indicates the core was under reset; reject those tokens
val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ") val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).filter(line =>
val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength) (line.last.toInt & 1) == 0)
assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1,
s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}") s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}")
assert(verilatedOutput.nonEmpty) assert(verilatedOutput.nonEmpty)