From 924f4403850df60edc533d83140225e161c248bf Mon Sep 17 00:00:00 2001
From: David Biancolin <david.biancolin@gmail.com>
Date: Mon, 20 Jan 2020 12:00:23 -0800
Subject: [PATCH] [Firechip] Include reset in tracerv tokens

---
 .../src/main/scala/TargetMixins.scala         |  9 ++++++---
 .../src/test/scala/ScalaTestSuite.scala       | 19 ++++++++++---------
 2 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala
index 50d51269..d7714527 100644
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -42,10 +42,13 @@ trait HasTraceIOImp extends LazyModuleImp {
   outer.tileTraceNodes.zipWithIndex.foreach({ case (node, idx) =>
     if (p(InstantiateTracerVBridges)) {
       val b = TracerVBridge(node.bundle)
+      // Used for verifying the TracerV bridge
       if (p(PrintTracePort)) {
-        val traceprint = WireDefault(0.U(512.W))
-        traceprint := b.io.traces.asUInt
-        printf(s"TRACEPORT ${idx}: %x\n", traceprint)
+        withClockAndReset(node.bundle.head.clock, node.bundle.head.reset) {
+          val traceprint = WireDefault(0.U(512.W))
+          traceprint := b.io.traces.asUInt
+          printf(s"TRACEPORT ${idx}: %x\n", traceprint)
+        }
       }
     }
   })
diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala
index 7f505ab1..9a8da363 100644
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -106,15 +106,16 @@ abstract class FireSimTestSuite(
   def diffTracelog(verilatedLog: String) {
     behavior of "captured instruction trace"
     it should s"match the chisel printf in ${verilatedLog}" in {
-      def getLines(file: File, dropLines: Int = 0, prefixFilter: String = ""): Seq[String] = {
-        val lines = Source.fromFile(file).getLines.toList
-        lines.filter(_.startsWith(prefixFilter))
-             .drop(dropLines)
-             .map(_.stripPrefix(prefixFilter))
-      }
-      val resetLength = 51
-      val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"), prefixFilter = "TRACEPORT 0: ")
-      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), dropLines = resetLength)
+      def getLines(file: File): Seq[String] = Source.fromFile(file).getLines.toList
+
+      val printfPrefix =  "TRACEPORT 0: "
+      val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}")).collect({
+        case line if line.startsWith(printfPrefix) => line.stripPrefix(printfPrefix) })
+
+      // Last bit indicates the core was under reset; reject those tokens
+      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE")).filter(line =>
+        (line.last.toInt & 1) == 0)
+
       assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1,
         s"\nPrintf Length: ${verilatedOutput.size}, Trace Length: ${synthPrintOutput.size}")
       assert(verilatedOutput.nonEmpty)