Merge remote-tracking branch 'origin/goldengate-firrtl-stage' into dev

build.sbt

@@ -23,6 +23,7 @@ lazy val commonSettings = Seq(
   addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
   unmanagedBase := (chipyardRoot / unmanagedBase).value,
   allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"),
+  exportJars := true,
   resolvers ++= Seq(
     Resolver.sonatypeRepo("snapshots"),
     Resolver.sonatypeRepo("releases"),

docs/Simulation/FPGA-Accelerated-Simulators.rst

@@ -87,4 +87,4 @@ will look as follows:
 You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG``
 variables. Note that if your target machine has I/O not provided in the default
 FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need
-to write a custom endpoint.
+to write a custom bridge.

generators/firechip/src/main/scala/BridgeBinders.scala

@@ -0,0 +1,76 @@
+//See LICENSE for license details.
+
+package firesim.firesim
+
+import chisel3._
+
+import freechips.rocketchip.config.{Field, Config}
+import freechips.rocketchip.diplomacy.{LazyModule}
+import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
+import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
+import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
+
+import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
+import icenet.HasPeripheryIceNICModuleImpValidOnly
+
+import junctions.{NastiKey, NastiParameters}
+import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
+import firesim.bridges._
+import firesim.configs.MemModelKey
+import firesim.util.RegisterBridgeBinder
+
+class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
+  target.debug.clockeddmi.foreach({ cdmi =>
+    cdmi.dmi.req.valid := false.B
+    cdmi.dmi.req.bits := DontCare
+    cdmi.dmi.resp.ready := false.B
+    cdmi.dmiClock := false.B.asClock
+    cdmi.dmiReset := false.B
+  })
+  Seq()
+})
+
+class WithSerialBridge extends RegisterBridgeBinder({
+  case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) 
+})
+
+class WithNICBridge extends RegisterBridgeBinder({
+  case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) 
+})
+
+class WithUARTBridge extends RegisterBridgeBinder({
+  case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) 
+})
+
+class WithBlockDeviceBridge extends RegisterBridgeBinder({
+  case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) 
+})
+
+class WithFASEDBridge extends RegisterBridgeBinder({
+  case t: CanHaveMasterAXI4MemPortModuleImp =>
+    implicit val p = t.p
+    (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
+      (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
+        val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
+                                       axi4Bundle.ar.bits.addr.getWidth,
+                                       axi4Bundle.ar.bits.id.getWidth)
+        FASEDBridge(axi4Bundle, t.reset.toBool,
+          CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
+      })
+    }).toSeq
+})
+
+class WithTracerVBridge extends RegisterBridgeBinder({
+  case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
+})
+
+// Shorthand to register all of the provided bridges above
+class WithDefaultFireSimBridges extends Config(
+  new WithTiedOffDebug ++
+  new WithSerialBridge ++
+  new WithNICBridge ++
+  new WithUARTBridge ++
+  new WithBlockDeviceBridge ++
+  new WithFASEDBridge ++
+  new WithTracerVBridge
+)

generators/firechip/src/main/scala/EndpointBinders.scala

@@ -1,80 +0,0 @@
-//See LICENSE for license details.
-
-package firesim.firesim
-
-import chisel3._
-
-import freechips.rocketchip.config.{Field, Config}
-import freechips.rocketchip.diplomacy.{LazyModule}
-import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
-import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
-
-import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
-import icenet.HasPeripheryIceNICModuleImpValidOnly
-
-import junctions.{NastiKey, NastiParameters}
-import midas.widgets.{IsEndpoint}
-import midas.models.{FASEDEndpoint, FasedAXI4Edge}
-import firesim.endpoints._
-import firesim.configs.MemModelKey
-import firesim.util.RegisterEndpointBinder
-
-class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp =>
-  target.debug.clockeddmi.foreach({ cdmi =>
-    cdmi.dmi.req.valid := false.B
-    cdmi.dmi.req.bits := DontCare
-    cdmi.dmi.resp.ready := false.B
-    cdmi.dmiClock := false.B.asClock
-    cdmi.dmiReset := false.B
-  })
-  Seq()
-})
-
-class WithSerialEndpoint extends RegisterEndpointBinder({
-  case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p)) 
-})
-
-class WithNICEndpoint extends RegisterEndpointBinder({
-  case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p)) 
-})
-
-class WithUARTEndpoint extends RegisterEndpointBinder({
-  case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p)) 
-})
-
-class WithBlockDeviceEndpoint extends RegisterEndpointBinder({
-  case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p)) 
-})
-
-class WithFASEDEndpoint extends RegisterEndpointBinder({
-  case t: CanHaveMasterAXI4MemPortModuleImp =>
-    implicit val p = t.p
-    (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
-      (io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
-        val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
-                                       axi4Bundle.ar.bits.addr.getWidth,
-                                       axi4Bundle.ar.bits.id.getWidth)
-        val fasedP = p.alterPartial({
-          case NastiKey => nastiKey
-          case FasedAXI4Edge => Some(edge)
-        })
-        FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP)
-      })
-    }).toSeq
-})
-
-class WithTracerVEndpoint extends RegisterEndpointBinder({
-  case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p)
-})
-
-// Shorthand to register all of the provided endpoints above
-class WithDefaultFireSimEndpoints extends Config(
-  new WithTiedOffDebug ++
-  new WithSerialEndpoint ++
-  new WithNICEndpoint ++
-  new WithUARTEndpoint ++
-  new WithBlockDeviceEndpoint ++
-  new WithFASEDEndpoint ++
-  new WithTracerVEndpoint
-)

generators/firechip/src/main/scala/Generator.scala

@@ -2,7 +2,7 @@
 
 package firesim.firesim
 
-import java.io.{File}
+import java.io.{File, FileWriter}
 
 import chisel3.experimental.RawModule
 import chisel3.internal.firrtl.{Circuit, Port}
@@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
 }
 
 object FireSimGenerator extends App with IsFireSimGeneratorLike {
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
   lazy val generatorArgs = GeneratorArgs(args)
   lazy val genDir = new File(names.targetDir)
-  elaborateAndCompileWithMidas
+  // The only reason this is not generateFirrtl; generateAnno is that we need to use a different 
+  // JsonProtocol to properly write out the annotations. Fix once the generated are unified
+  elaborate
   generateTestSuiteMakefrags
-  generateHostVerilogHeader
   generateArtefacts
-  generateTclEnvFile
 }
 
 // For now, provide a separate generator app when not specifically building for FireSim

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -18,7 +18,7 @@ import scala.math.{min, max}
 import tracegen.TraceGenKey
 import icenet._
 
-import firesim.endpoints._
+import firesim.bridges._
 import firesim.util.{WithNumNodes}
 import firesim.configs._
 
@@ -113,7 +113,7 @@ class FireSimRocketChipConfig extends Config(
   new WithPerfCounters ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++
-  new WithDefaultFireSimEndpoints ++
+  new WithDefaultFireSimBridges ++
   new freechips.rocketchip.system.DefaultConfig)
 
 class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
@@ -163,7 +163,7 @@ class FireSimBoomConfig extends Config(
   new WithDefaultMemModel ++
   new boom.common.WithLargeBooms ++
   new boom.common.WithNBoomCores(1) ++
-  new WithDefaultFireSimEndpoints ++
+  new WithDefaultFireSimBridges ++
   new freechips.rocketchip.system.BaseConfig
 )
 

generators/firechip/src/main/scala/TargetMixins.scala

@@ -11,12 +11,12 @@ import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.util._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.rocket.TracedInstruction
-import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
+import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
 
 import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
 
 /* Wires out tile trace ports to the top; and wraps them in a Bundle that the
- * TracerV endpoint can match on.
+ * TracerV bridge can match on.
  */
 object PrintTracePort extends Field[Boolean](false)
 

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -23,6 +23,8 @@ abstract class FireSimTestSuite(
   import scala.concurrent.duration._
   import ExecutionContext.Implicits.global
 
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+
   lazy val generatorArgs = GeneratorArgs(
     midasFlowKind = "midas",
     targetDir = "generated-src",
@@ -42,7 +44,6 @@ abstract class FireSimTestSuite(
   val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
                            s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
                            s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
-  override lazy val platform = hostParams(midas.Platform)
 
   def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
     make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
@@ -122,7 +123,7 @@ abstract class FireSimTestSuite(
 
   clean
   mkdirs
-  elaborateAndCompileWithMidas
+  elaborate
   generateTestSuiteMakefrags
   runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0"""))
   diffTracelog("rv64ui-p-simple.out")