From 53f58f6baa21f2cf2c818f0cdbea8004f181d23e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Sep 2019 15:41:21 -0700 Subject: [PATCH 1/4] Support serializable endpoints; Golden Gate stage --- build.sbt | 1 + .../firechip/src/main/scala/EndpointBinders.scala | 10 +++------- generators/firechip/src/main/scala/Generator.scala | 9 +++++---- .../firechip/src/test/scala/ScalaTestSuite.scala | 5 +++-- sims/firesim | 2 +- vlsi/hammer | 2 +- 6 files changed, 14 insertions(+), 15 deletions(-) diff --git a/build.sbt b/build.sbt index 4d747829..ccc9e87f 100644 --- a/build.sbt +++ b/build.sbt @@ -23,6 +23,7 @@ lazy val commonSettings = Seq( addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), + exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), Resolver.sonatypeRepo("releases"), diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala index 0450f8f3..cc76503d 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -14,8 +14,7 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint} -import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig} import firesim.endpoints._ import firesim.configs.MemModelKey import firesim.util.RegisterEndpointBinder @@ -55,11 +54,8 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - val fasedP = p.alterPartial({ - case NastiKey => nastiKey - case FasedAXI4Edge => Some(edge) - }) - FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP) + FASEDEndpoint(axi4Bundle, t.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq }) diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 169cbe1f..0c5b4909 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -2,7 +2,7 @@ package firesim.firesim -import java.io.{File} +import java.io.{File, FileWriter} import chisel3.experimental.RawModule import chisel3.internal.firrtl.{Circuit, Port} @@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu } object FireSimGenerator extends App with IsFireSimGeneratorLike { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs lazy val generatorArgs = GeneratorArgs(args) lazy val genDir = new File(names.targetDir) - elaborateAndCompileWithMidas + // The only reason this is not generateFirrtl; generateAnno is that we need to use a different + // JsonProtocol to properly write out the annotations. Fix once the generated are unified + elaborate generateTestSuiteMakefrags - generateHostVerilogHeader generateArtefacts - generateTclEnvFile } // For now, provide a separate generator app when not specifically building for FireSim diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index e7194d8c..0cda4b93 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -23,6 +23,8 @@ abstract class FireSimTestSuite( import scala.concurrent.duration._ import ExecutionContext.Implicits.global + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + lazy val generatorArgs = GeneratorArgs( midasFlowKind = "midas", targetDir = "generated-src", @@ -42,7 +44,6 @@ abstract class FireSimTestSuite( val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", s"TARGET_CONFIG=${generatorArgs.targetConfigs}", s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") - override lazy val platform = hostParams(midas.Platform) def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), @@ -122,7 +123,7 @@ abstract class FireSimTestSuite( clean mkdirs - elaborateAndCompileWithMidas + elaborate generateTestSuiteMakefrags runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0""")) diffTracelog("rv64ui-p-simple.out") diff --git a/sims/firesim b/sims/firesim index 4c1a3aa2..a94bea1d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 +Subproject commit a94bea1d16e858c4b04d03306fb100962b09dc9a diff --git a/vlsi/hammer b/vlsi/hammer index 1b07b9a3..a27886fb 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 +Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 From ad76e0ad1c735862e49f3009d54f82f006721e71 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 3 Oct 2019 15:56:05 -0700 Subject: [PATCH 2/4] Bump FireSim; Revert an errant hammer bump --- sims/firesim | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index a94bea1d..9bd6679e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a94bea1d16e858c4b04d03306fb100962b09dc9a +Subproject commit 9bd6679ea8d3f7d3e99e827d1cd27322d7b498b1 diff --git a/vlsi/hammer b/vlsi/hammer index a27886fb..1b07b9a3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 +Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 From aa6e09f80056852e52a4a9d21161f558ebeb90f8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 03:32:50 +0000 Subject: [PATCH 3/4] Rename Endpoint -> Bridge --- .../FPGA-Accelerated-Simulators.rst | 2 +- ...pointBinders.scala => BridgeBinders.scala} | 48 +++++++++---------- .../src/main/scala/TargetConfigs.scala | 6 +-- .../src/main/scala/TargetMixins.scala | 4 +- 4 files changed, 30 insertions(+), 30 deletions(-) rename generators/firechip/src/main/scala/{EndpointBinders.scala => BridgeBinders.scala} (52%) diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index 29f42880..c8640f9d 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -87,4 +87,4 @@ will look as follows: You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` variables. Note that if your target machine has I/O not provided in the default FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need -to write a custom endpoint. +to write a custom bridge. diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala similarity index 52% rename from generators/firechip/src/main/scala/EndpointBinders.scala rename to generators/firechip/src/main/scala/BridgeBinders.scala index cc76503d..c2bed0e5 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -14,12 +14,12 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig} -import firesim.endpoints._ +import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} +import firesim.bridges._ import firesim.configs.MemModelKey -import firesim.util.RegisterEndpointBinder +import firesim.util.RegisterBridgeBinder -class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => +class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp => target.debug.clockeddmi.foreach({ cdmi => cdmi.dmi.req.valid := false.B cdmi.dmi.req.bits := DontCare @@ -30,23 +30,23 @@ class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripher Seq() }) -class WithSerialEndpoint extends RegisterEndpointBinder({ - case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p)) +class WithSerialBridge extends RegisterBridgeBinder({ + case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) }) -class WithNICEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p)) +class WithNICBridge extends RegisterBridgeBinder({ + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) }) -class WithUARTEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p)) +class WithUARTBridge extends RegisterBridgeBinder({ + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) }) -class WithBlockDeviceEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p)) +class WithBlockDeviceBridge extends RegisterBridgeBinder({ + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) }) -class WithFASEDEndpoint extends RegisterEndpointBinder({ +class WithFASEDBridge extends RegisterBridgeBinder({ case t: CanHaveMasterAXI4MemPortModuleImp => implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -54,23 +54,23 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDEndpoint(axi4Bundle, t.reset.toBool, + FASEDBridge(axi4Bundle, t.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq }) -class WithTracerVEndpoint extends RegisterEndpointBinder({ - case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p) +class WithTracerVBridge extends RegisterBridgeBinder({ + case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) }) -// Shorthand to register all of the provided endpoints above -class WithDefaultFireSimEndpoints extends Config( +// Shorthand to register all of the provided bridges above +class WithDefaultFireSimBridges extends Config( new WithTiedOffDebug ++ - new WithSerialEndpoint ++ - new WithNICEndpoint ++ - new WithUARTEndpoint ++ - new WithBlockDeviceEndpoint ++ - new WithFASEDEndpoint ++ - new WithTracerVEndpoint + new WithSerialBridge ++ + new WithNICBridge ++ + new WithUARTBridge ++ + new WithBlockDeviceBridge ++ + new WithFASEDBridge ++ + new WithTracerVBridge ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d0c55ed3..689927b0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -18,7 +18,7 @@ import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ -import firesim.endpoints._ +import firesim.bridges._ import firesim.util.{WithNumNodes} import firesim.configs._ @@ -113,7 +113,7 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithDefaultFireSimEndpoints ++ + new WithDefaultFireSimBridges ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -163,7 +163,7 @@ class FireSimBoomConfig extends Config( new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ - new WithDefaultFireSimEndpoints ++ + new WithDefaultFireSimBridges ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 0c7d2eb9..43d03853 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -11,12 +11,12 @@ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.util._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction -import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} /* Wires out tile trace ports to the top; and wraps them in a Bundle that the - * TracerV endpoint can match on. + * TracerV bridge can match on. */ object PrintTracePort extends Field[Boolean](false) From 115102c987f9400bead34d99808ffcbb9050c91d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 03:36:12 +0000 Subject: [PATCH 4/4] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 9bd6679e..a1f3a927 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9bd6679ea8d3f7d3e99e827d1cd27322d7b498b1 +Subproject commit a1f3a927a975dea1200a56260c140998866a1c51