remove SimpleNIC
This commit is contained in:
25
README.md
25
README.md
@@ -72,31 +72,6 @@ By passing the +blkdev argument on the simulator command line, you can allow
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the RTL simulation to read and write from a file. Take a look at tests/blkdev.c
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the RTL simulation to read and write from a file. Take a look at tests/blkdev.c
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for an example of how Rocket can program the block device controller.
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for an example of how Rocket can program the block device controller.
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## Using the network device
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Testchipip also includes a basic ethernet controller (SimpleNIC). The simulator
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provides a way to connect this up to a tap interface and thus interact with
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rocketchip as if it was a regular network node.
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First set up the tap interface. If you want to run the simulation as a regular
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user (recommended), use the following commands.
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sudo ip tuntap add mode tap dev tap0 user $USER
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sudo ip link set tap0 up
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sudo ip addr add 192.168.1.1/24 dev tap0
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Then build the SimNetworkConfig and pass it the name of the tap interface
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make CONFIG=SimNetworkConfig
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./simulator-example-SimNetworkConfig +netdev=tap0 ../tests/pingd.riscv
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Then run ping in a separate terminal.
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ping 192.168.1.2
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You should now see the ping responses come back. The `pingd.riscv` program
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will also log each packet it receives.
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## Adding an MMIO peripheral
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## Adding an MMIO peripheral
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You can RocketChip to create your own memory-mapped IO device and add it into
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You can RocketChip to create your own memory-mapped IO device and add it into
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@@ -33,22 +33,6 @@ class WithSimBlockDevice extends Config((site, here, up) => {
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}
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}
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})
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})
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class WithLoopbackNIC extends Config((site, here, up) => {
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case BuildTop => (p: Parameters) => {
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val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
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top.connectNicLoopback()
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top
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}
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})
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class WithSimNetwork extends Config((site, here, up) => {
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case BuildTop => (p: Parameters) => {
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val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
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top.connectSimNetwork()
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top
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}
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})
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class BaseExampleConfig extends Config(
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class BaseExampleConfig extends Config(
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new freechips.rocketchip.chip.DefaultConfig)
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new freechips.rocketchip.chip.DefaultConfig)
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@@ -66,12 +50,6 @@ class SimBlockDeviceConfig extends Config(
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class BlockDeviceModelConfig extends Config(
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class BlockDeviceModelConfig extends Config(
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new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
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new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
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class LoopbackNICConfig extends Config(
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new WithLoopbackNIC ++ new BaseExampleConfig)
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class SimNetworkConfig extends Config(
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new WithSimNetwork ++ new BaseExampleConfig)
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class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
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class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
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class WithFourTrackers extends WithNBlockDeviceTrackers(4)
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class WithFourTrackers extends WithNBlockDeviceTrackers(4)
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@@ -41,12 +41,3 @@ class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop
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class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
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class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
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extends ExampleTopModule(l)
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extends ExampleTopModule(l)
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with HasPeripheryBlockDeviceModuleImp
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with HasPeripheryBlockDeviceModuleImp
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class ExampleTopWithSimpleNIC(implicit p: Parameters) extends ExampleTop
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with HasPeripherySimpleNIC {
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override lazy val module = new ExampleTopWithSimpleNICModule(this)
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}
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class ExampleTopWithSimpleNICModule(outer: ExampleTopWithSimpleNIC)
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extends ExampleTopModule(outer)
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with HasPeripherySimpleNICModuleImp
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Submodule testchipip updated: db0bd0fe6e...fa3dd9ab08
@@ -27,14 +27,11 @@ sim_vsrcs = \
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$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
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$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
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$(base_dir)/testchipip/vsrc/SimSerial.v \
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$(base_dir)/testchipip/vsrc/SimSerial.v \
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$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
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$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
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$(base_dir)/testchipip/vsrc/SimNetwork.v
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sim_csrcs = \
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sim_csrcs = \
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$(base_dir)/testchipip/csrc/SimSerial.cc \
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$(base_dir)/testchipip/csrc/SimSerial.cc \
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$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
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$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
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$(base_dir)/testchipip/csrc/SimNetwork.cc \
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$(base_dir)/testchipip/csrc/blkdev.cc \
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$(base_dir)/testchipip/csrc/blkdev.cc \
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$(base_dir)/testchipip/csrc/network.cc \
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$(base_dir)/testchipip/csrc/verilator-harness.cc
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$(base_dir)/testchipip/csrc/verilator-harness.cc
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model_dir = $(build_dir)/$(long_name)
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model_dir = $(build_dir)/$(long_name)
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@@ -23,14 +23,11 @@ sim_vsrcs = \
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$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
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$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
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$(base_dir)/testchipip/vsrc/SimSerial.v \
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$(base_dir)/testchipip/vsrc/SimSerial.v \
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$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
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$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
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$(base_dir)/testchipip/vsrc/SimNetwork.v \
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sim_csrcs = \
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sim_csrcs = \
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$(base_dir)/testchipip/csrc/SimSerial.cc \
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$(base_dir)/testchipip/csrc/SimSerial.cc \
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$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
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$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
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$(base_dir)/testchipip/csrc/SimNetwork.cc \
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$(base_dir)/testchipip/csrc/blkdev.cc \
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$(base_dir)/testchipip/csrc/blkdev.cc \
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$(base_dir)/testchipip/csrc/network.cc \
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VCS = vcs -full64
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VCS = vcs -full64
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