diff --git a/README.md b/README.md
index 394ebf65..02ed3847 100644
--- a/README.md
+++ b/README.md
@@ -72,31 +72,6 @@ By passing the +blkdev argument on the simulator command line, you can allow
 the RTL simulation to read and write from a file. Take a look at tests/blkdev.c
 for an example of how Rocket can program the block device controller.
 
-## Using the network device
-
-Testchipip also includes a basic ethernet controller (SimpleNIC). The simulator
-provides a way to connect this up to a tap interface and thus interact with
-rocketchip as if it was a regular network node.
-
-First set up the tap interface. If you want to run the simulation as a regular
-user (recommended), use the following commands.
-
-    sudo ip tuntap add mode tap dev tap0 user $USER
-    sudo ip link set tap0 up
-    sudo ip addr add 192.168.1.1/24 dev tap0
-
-Then build the SimNetworkConfig and pass it the name of the tap interface
-
-    make CONFIG=SimNetworkConfig
-    ./simulator-example-SimNetworkConfig +netdev=tap0 ../tests/pingd.riscv
-
-Then run ping in a separate terminal.
-
-    ping 192.168.1.2
-
-You should now see the ping responses come back. The `pingd.riscv` program
-will also log each packet it receives.
-
 ## Adding an MMIO peripheral
 
 You can RocketChip to create your own memory-mapped IO device and add it into
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index 6e91fb26..3c126268 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -33,22 +33,6 @@ class WithSimBlockDevice extends Config((site, here, up) => {
   }
 })
 
-class WithLoopbackNIC extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => {
-    val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
-    top.connectNicLoopback()
-    top
-  }
-})
-
-class WithSimNetwork extends Config((site, here, up) => {
-  case BuildTop => (p: Parameters) => {
-    val top = Module(LazyModule(new ExampleTopWithSimpleNIC()(p)).module)
-    top.connectSimNetwork()
-    top
-  }
-})
-
 class BaseExampleConfig extends Config(
   new freechips.rocketchip.chip.DefaultConfig)
 
@@ -66,12 +50,6 @@ class SimBlockDeviceConfig extends Config(
 class BlockDeviceModelConfig extends Config(
   new WithBlockDevice ++ new WithBlockDeviceModel ++ new BaseExampleConfig)
 
-class LoopbackNICConfig extends Config(
-  new WithLoopbackNIC ++ new BaseExampleConfig)
-
-class SimNetworkConfig extends Config(
-  new WithSimNetwork ++ new BaseExampleConfig)
-
 class WithTwoTrackers extends WithNBlockDeviceTrackers(2)
 class WithFourTrackers extends WithNBlockDeviceTrackers(4)
 
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index 1684d002..16c148b7 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -41,12 +41,3 @@ class ExampleTopWithBlockDevice(implicit p: Parameters) extends ExampleTop
 class ExampleTopWithBlockDeviceModule(l: ExampleTopWithBlockDevice)
   extends ExampleTopModule(l)
   with HasPeripheryBlockDeviceModuleImp
-
-class ExampleTopWithSimpleNIC(implicit p: Parameters) extends ExampleTop
-    with HasPeripherySimpleNIC {
-  override lazy val module = new ExampleTopWithSimpleNICModule(this)
-}
-
-class ExampleTopWithSimpleNICModule(outer: ExampleTopWithSimpleNIC)
-  extends ExampleTopModule(outer)
-  with HasPeripherySimpleNICModuleImp
diff --git a/testchipip b/testchipip
index db0bd0fe..fa3dd9ab 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit db0bd0fe6ed3e7eb89eafea1a0ced103e2f781ee
+Subproject commit fa3dd9ab0844f8d23c76d1fd0abc28c671b1d06a
diff --git a/verisim/Makefile b/verisim/Makefile
index eaf7b7bf..afb75469 100644
--- a/verisim/Makefile
+++ b/verisim/Makefile
@@ -27,14 +27,11 @@ sim_vsrcs = \
 	$(base_dir)/rocket-chip/vsrc/AsyncResetReg.v \
 	$(base_dir)/testchipip/vsrc/SimSerial.v \
 	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
-	$(base_dir)/testchipip/vsrc/SimNetwork.v
 
 sim_csrcs = \
 	$(base_dir)/testchipip/csrc/SimSerial.cc \
 	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
-	$(base_dir)/testchipip/csrc/SimNetwork.cc \
 	$(base_dir)/testchipip/csrc/blkdev.cc \
-	$(base_dir)/testchipip/csrc/network.cc \
 	$(base_dir)/testchipip/csrc/verilator-harness.cc
 
 model_dir = $(build_dir)/$(long_name)
diff --git a/vsim/Makefile b/vsim/Makefile
index d9f85e30..eb5a7026 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -23,14 +23,11 @@ sim_vsrcs = \
 	$(base_dir)/rocket-chip/vsrc/plusarg_reader.v \
 	$(base_dir)/testchipip/vsrc/SimSerial.v \
 	$(base_dir)/testchipip/vsrc/SimBlockDevice.v \
-	$(base_dir)/testchipip/vsrc/SimNetwork.v \
 
 sim_csrcs = \
 	$(base_dir)/testchipip/csrc/SimSerial.cc \
 	$(base_dir)/testchipip/csrc/SimBlockDevice.cc \
-	$(base_dir)/testchipip/csrc/SimNetwork.cc \
 	$(base_dir)/testchipip/csrc/blkdev.cc \
-	$(base_dir)/testchipip/csrc/network.cc \
 
 VCS = vcs -full64