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Bump rocket-chip for Coalescing supporting N threads

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This commit is contained in:
Vamber Yang
2023-03-03 20:51:55 -08:00
parent d2569bf175 ad0e9c8914
commit 8f43d54bfe
15 changed files with 91 additions and 58 deletions
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4
build.sbt
View File

@@ -173,7 +173,7 @@ lazy val tracegen = (project in file("generators/tracegen"))
.settings(commonSettings)
lazy val icenet = (project in file("generators/icenet"))
.dependsOn(testchipip, rocketchip)
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -209,7 +209,7 @@ lazy val sha3 = (project in file("generators/sha3"))
.settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(testchipip, rocketchip)
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(chiselTestSettings)
.settings(commonSettings)

32
common.mk
View File

@@ -126,10 +126,20 @@ define mfc_extra_anno_contents
}
]
endef
define sfc_extra_low_transforms_anno_contents
[
{
"class": "firrtl.stage.RunFirrtlTransformAnnotation",
"transform": "barstools.tapeout.transforms.ExtraLowTransforms"
}
]
endef
export mfc_extra_anno_contents
$(FINAL_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE): $(ANNO_FILE)
export sfc_extra_low_transforms_anno_contents
$(EXTRA_ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) &: $(ANNO_FILE)
echo "$$mfc_extra_anno_contents" > $(MFC_EXTRA_ANNO_FILE)
jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE)
echo "$$sfc_extra_low_transforms_anno_contents" > $(SFC_EXTRA_ANNO_FILE)
jq -s '[.[][]]' $(ANNO_FILE) $(MFC_EXTRA_ANNO_FILE) > $(EXTRA_ANNO_FILE)
.PHONY: firrtl
firrtl: $(FIRRTL_FILE) $(FINAL_ANNO_FILE)
@@ -149,7 +159,6 @@ SFC_MFC_TARGETS = \
SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
# DOC include start: FirrtlCompiler
# There are two possible cases for this step. In the first case, SFC
# compiles Chisel to CHIRRTL, and MFC compiles CHIRRTL to Verilog. Otherwise,
@@ -161,8 +170,7 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
# hack: lower to low firrtl if Fixed types are found
# hack: when using dontTouch, io.cpu annotations are not removed by SFC,
# hence we remove them manually by using jq before passing them to firtool
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES)
rm -rf $(GEN_COLLATERAL_DIR)
$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
@@ -170,6 +178,11 @@ else
$(eval SFC_LEVEL := low)
$(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM))
endif
if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
rm -rf $(GEN_COLLATERAL_DIR)
$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
--no-dedup \
--output-file $(SFC_FIRRTL_BASENAME) \
@@ -179,13 +192,12 @@ endif
--annotation-file $(FINAL_ANNO_FILE) \
--log-level $(FIRRTL_LOGLEVEL) \
--allow-unrecognized-annotations \
-DX $(SFC_LEVEL) \
-X $(SFC_LEVEL) \
$(EXTRA_FIRRTL_OPTIONS)) # -X and -DX are duplicates to allow for extra FIRRTL passes to be run
$(EXTRA_FIRRTL_OPTIONS))
-mv $(SFC_FIRRTL_BASENAME).lo.fir $(SFC_FIRRTL_FILE) # Optionally change file type when SFC generates LowFIRRTL
@if [ "$(SFC_LEVEL)" = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi
@if [ "$(SFC_LEVEL)" = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi
@if [ $(SFC_LEVEL) = low ]; then cat $(SFC_ANNO_FILE) | jq 'del(.[] | select(.target | test("io.cpu"))?)' > /tmp/unnec-anno-deleted.sfc.anno.json; fi
@if [ $(SFC_LEVEL) = low ]; then cat /tmp/unnec-anno-deleted.sfc.anno.json | jq 'del(.[] | select(.class | test("SRAMAnnotation"))?)' > /tmp/unnec-anno-deleted2.sfc.anno.json; fi
@if [ $(SFC_LEVEL) = low ]; then cat /tmp/unnec-anno-deleted2.sfc.anno.json > $(SFC_ANNO_FILE) && rm /tmp/unnec-anno-deleted.sfc.anno.json && rm /tmp/unnec-anno-deleted2.sfc.anno.json; fi
firtool \
--format=fir \
--dedup \

2
docs/Customization/DMA-Devices.rst
View File

@@ -20,7 +20,7 @@ that writes zeros to the memory at a configured address.
:start-after: DOC include start: DigitalTop
:end-before: DOC include end: DigitalTop
We use ``TLHelper.makeClientNode`` to create a TileLink client node for us.
We use ``TLClientNode`` to create a TileLink client node for us.
We then connect the client node to the memory system through the front bus (fbus).
For more info on creating TileLink client nodes, take a look at :ref:`TileLink-Diplomacy-Reference/NodeTypes:Client Node`.

9
docs/TileLink-Diplomacy-Reference/NodeTypes.rst
View File

@@ -16,8 +16,7 @@ on the C channel, and send grant acknowledgements on the E channel.
The L1 caches and DMA devices in RocketChip/Chipyard have client nodes.
You can add a TileLink client node to your LazyModule using the TLHelper
object from testchipip like so:
You can add a TileLink client node to your LazyModule like so:
.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala
:language: scala
@@ -48,8 +47,7 @@ generators optimize the hardware by not arbitrating the client to managers with
address ranges that don't overlap with its visibility.
Inside your lazy module implementation, you can call ``node.out`` to get a
list of bundle/edge pairs. If you used the TLHelper, you only specified a
single client edge, so this list will only have one pair.
list of bundle/edge pairs.
The ``tl`` bundle is a Chisel hardware bundle that connects to the IO of this
module. It contains two (in the case of TL-UL and TL-UH) or five (in the case
@@ -65,8 +63,7 @@ Manager Node
------------
TileLink managers take requests from clients on the A channel and send
responses back on the D channel. You can create a manager node using the
TLHelper like so:
responses back on the D channel. You can create a manager like so:
.. literalinclude:: ../../generators/chipyard/src/main/scala/example/NodeTypes.scala
:language: scala

12
docs/VLSI/Advanced-Usage.rst
View File

@@ -3,14 +3,22 @@
Advanced Usage
==============
Hammer Development
------------------
Hammer Development and Upgrades
-------------------------------
If you need to develop Hammer within Chipyard or use a version of Hammer beyond the latest PyPI release, clone the `Hammer repository <https://github.com/ucb-bar/hammer>`__ somewhere else on your disk. Then:
.. code-block:: shell
pip install -e <path/to/hammer>
To bump specific plugins to their latest commits and install them, you can use the upgrade script from the Chipyard root directory, with arguments for match patterns for the plugin names:
.. code-block:: shell
./scripts/upgrade-vlsi.sh <pattern(s)>
If you would like to upgrade your Hammer installation to the latest PyPI release and bump all of your plugins at once, run the above script without arguments. WARNING: this may pull in plugin changes that are newer than the latest Hammer release and cause incompatibility issues.
Alternative RTL Flows
---------------------
The Make-based build system provided supports using Hammer without using RTL generated by Chipyard. To push a custom Verilog module through, one only needs to append the following environment variables to the ``make buildfile`` command (or edit them directly in the Makefile).

6
generators/chipyard/src/main/scala/example/InitZero.scala
View File

@@ -5,14 +5,14 @@ import chisel3.util._
import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
import freechips.rocketchip.config.{Parameters, Field, Config}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
import testchipip.TLHelper
import freechips.rocketchip.tilelink._
case class InitZeroConfig(base: BigInt, size: BigInt)
case object InitZeroKey extends Field[Option[InitZeroConfig]](None)
class InitZero(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode(
name = "init-zero", sourceId = IdRange(0, 1))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "init-zero", sourceId = IdRange(0, 1))))))
lazy val module = new InitZeroModuleImp(this)
}

23
generators/chipyard/src/main/scala/example/NodeTypes.scala
View File

@@ -3,7 +3,6 @@ package chipyard.example
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import testchipip.TLHelper
// These modules are not meant to be synthesized.
// They are used as examples in the documentation and are only here
@@ -11,11 +10,11 @@ import testchipip.TLHelper
// DOC include start: MyClient
class MyClient(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode(TLMasterParameters.v1(
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
name = "my-client",
sourceId = IdRange(0, 4),
requestFifo = true,
visibility = Seq(AddressSet(0x10000, 0xffff))))
visibility = Seq(AddressSet(0x10000, 0xffff)))))))
lazy val module = new LazyModuleImp(this) {
val (tl, edge) = node.out(0)
@@ -29,7 +28,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
class MyManager(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
val beatBytes = 8
val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
address = Seq(AddressSet(0x20000, 0xfff)),
resources = device.reg,
regionType = RegionType.UNCACHED,
@@ -40,7 +39,7 @@ class MyManager(implicit p: Parameters) extends LazyModule {
supportsPutFull = TransferSizes(1, beatBytes),
supportsPutPartial = TransferSizes(1, beatBytes),
supportsHint = TransferSizes(1, beatBytes),
fifoId = Some(0)))
fifoId = Some(0))), beatBytes)))
lazy val module = new LazyModuleImp(this) {
val (tl, edge) = node.in(0)
@@ -50,7 +49,8 @@ class MyManager(implicit p: Parameters) extends LazyModule {
// DOC include start: MyClient1+MyClient2
class MyClient1(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
"my-client1", IdRange(0, 1))))))
lazy val module = new LazyModuleImp(this) {
// ...
@@ -58,7 +58,8 @@ class MyClient1(implicit p: Parameters) extends LazyModule {
}
class MyClient2(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1))
val node = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLClientParameters(
"my-client2", IdRange(0, 1))))))
lazy val module = new LazyModuleImp(this) {
// ...
@@ -83,8 +84,8 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {
// DOC include start: MyManagerGroup
class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
address = Seq(AddressSet(0x0, 0xfff))))
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
address = Seq(AddressSet(0x0, 0xfff)))), beatBytes)))
lazy val module = new LazyModuleImp(this) {
// ...
@@ -92,8 +93,8 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
}
class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
address = Seq(AddressSet(0x1000, 0xfff))))
val node = TLManagerNode(Seq(TLSlavePortParameters.v1(Seq(TLManagerParameters(
address = Seq(AddressSet(0x1000, 0xfff)))), beatBytes)))
lazy val module = new LazyModuleImp(this) {
// ...

2
generators/chipyard/src/main/scala/stage/ChipyardAnnotations.scala
View File

@@ -13,7 +13,7 @@ private[stage] object UnderscoreDelimitedConfigsAnnotation extends HasShellOptio
longOption = "legacy-configs",
toAnnotationSeq = a => {
val split = a.split(':')
assert(split.length == 2)
assert(split.length == 2, s"'${a}' split by ':' doesn't yield two things")
val packageName = split.head
val configs = split.last.split("_")
Seq(new ConfigsAnnotation(configs map { config => if (config contains ".") s"${config}" else s"${packageName}.${config}" } ))

2
generators/gemmini

Submodule generators/gemmini updated: b6389f3ea7...9e478ecce9

2
generators/icenet

Submodule generators/icenet updated: fb23840eab...90d52a6a84

2
generators/testchipip

Submodule generators/testchipip updated: 2906d503cf...6e8a684242

2
scripts/tutorial-patches/build.sbt.patch
View File

@@ -27,4 +27,4 @@ index ec36a85f..c0c2849a 100644
+// .settings(commonSettings)
lazy val gemmini = (project in file("generators/gemmini"))
.dependsOn(testchipip, rocketchip)
.dependsOn(rocketchip)

47
scripts/upgrade-vlsi.sh
View File

@@ -1,8 +1,14 @@
#!/usr/bin/env bash
# This script updates Hammer and plugins.
# ./scripts/upgrade-vlsi.sh <pattern(s)> will upgrade plugins matching the pattern list.
# ./scripts/upgrade-vlsi.sh will upgrade all plugins and bump hammer-vlsi to the latest released version. Only do this upon a new Hammer release.
# exit script if any command fails
set -e
set -o pipefail
# except for grep in the pipe
clgrep() { grep $@ || test $? = 1; }
# exit script if not in Chipyard conda env
if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
@@ -11,24 +17,31 @@ if [[ `basename $CONDA_PREFIX` != .conda-env ]]; then
fi
# Get hammer submodules
package_names=$(git ls-files --stage | grep 160000 | awk '$4 ~/vlsi\/hammer.*/ {print $4}')
package_list=(${package_names})
plen="${#package_list[@]}"
if [[ ${plen} -gt 0 ]]; then
for p in "${package_list[@]}"; do
cd ${p}
echo "Updating current directory: $PWD"
git checkout `basename "$(git rev-parse --abbrev-ref origin/HEAD)"`
git pull
cd - > /dev/null
git add ${p}
pip install -e ${p} --upgrade
if [ $# -gt 0 ]; then
patterns=()
for arg in $@; do
patterns+=("-e" $arg)
done
package_list=($(git ls-files --stage | grep 160000 | clgrep ${patterns[@]} | awk '$4 ~/vlsi\/hammer.*/ {print $4}'))
else
package_list=($(git ls-files --stage | grep 160000 | awk '$4 ~/vlsi\/hammer.*/ {print $4}'))
# Also upgrade hammer-vlsi.
pip install hammer-vlsi --upgrade
fi
# Upgrade hammer-vlsi separately.
pip install hammer-vlsi --upgrade
# exit if requested package not found (case of an unmatched pattern in a list is not handled)
if [ -z ${package_list} ]; then
echo "No Hammer plugins matching these patterns found: $@"
exit
fi
# upgrade to latest commit in default branch
for p in ${package_list[@]}; do
echo "Updating ${p}"
cd ${p}
git checkout `basename "$(git rev-parse --abbrev-ref origin/HEAD)"`
git pull
cd - > /dev/null
git add ${p}
pip install -e ${p} --upgrade
done

2
tools/barstools

Submodule tools/barstools updated: 9760528f1d...30900965f0

2
variables.mk
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@@ -158,6 +158,7 @@ endif
# chisel generated outputs
FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
ANNO_FILE ?= $(build_dir)/$(long_name).anno.json
EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extra.anno.json
# chisel anno modification output
MFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrafirtool.anno.json
@@ -166,6 +167,7 @@ FINAL_ANNO_FILE ?= $(build_dir)/$(long_name).appended.anno.json
# scala firrtl compiler (sfc) outputs
SFC_FIRRTL_BASENAME ?= $(build_dir)/$(long_name).sfc
SFC_FIRRTL_FILE ?= $(SFC_FIRRTL_BASENAME).fir
SFC_EXTRA_ANNO_FILE ?= $(build_dir)/$(long_name).extrasfc.anno.json
SFC_ANNO_FILE ?= $(build_dir)/$(long_name).sfc.anno.json
# firtool compiler outputs