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Merge pull request #1372 from ucb-bar/add-disallowPackedArrays

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Add disallow packed arrays
This commit is contained in:
Abraham Gonzalez
2023-03-09 10:09:34 -08:00
committed by GitHub
parent 0af86430a9 1b7a424c69
commit 8f063139d8
2 changed files with 17 additions and 4 deletions
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12
common.mk
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@@ -18,6 +18,7 @@ HELP_COMPILATION_VARIABLES += \
" EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \
" ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
" ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \
" EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \
" EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler"
@@ -26,6 +27,7 @@ EXTRA_SIM_CXXFLAGS ?=
EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_LDFLAGS ?=
EXTRA_SIM_SOURCES ?= EXTRA_SIM_SOURCES ?=
EXTRA_SIM_REQS ?= EXTRA_SIM_REQS ?=
ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW)
#---------------------------------------------------------------------------- #----------------------------------------------------------------------------
HELP_SIMULATION_VARIABLES += \ HELP_SIMULATION_VARIABLES += \
@@ -159,6 +161,7 @@ SFC_MFC_TARGETS = \
$(GEN_COLLATERAL_DIR) $(GEN_COLLATERAL_DIR)
SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket
# DOC include start: FirrtlCompiler # DOC include start: FirrtlCompiler
# There are two possible cases for this step. In the first case, SFC # There are two possible cases for this step. In the first case, SFC
@@ -171,13 +174,18 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF)
# hack: lower to low firrtl if Fixed types are found # hack: lower to low firrtl if Fixed types are found
# hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hack: when using dontTouch, io.cpu annotations are not removed by SFC,
# hence we remove them manually by using jq before passing them to firtool # hence we remove them manually by using jq before passing them to firtool
$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE)
ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS))
$(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none))
$(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),))
else else
$(eval SFC_LEVEL := low) $(eval SFC_LEVEL := low)
$(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM))
endif
ifeq (,$(ENABLE_YOSYS_FLOW))
$(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS))
else
$(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays)
endif endif
if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
@@ -210,7 +218,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE
--disable-annotation-classless \ --disable-annotation-classless \
--disable-annotation-unknown \ --disable-annotation-unknown \
--mlir-timing \ --mlir-timing \
--lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ --lowering-options=$(MFC_LOWERING_OPTIONS) \
--repl-seq-mem \ --repl-seq-mem \
--repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \
--repl-seq-mem-circuit=$(MODEL) \ --repl-seq-mem-circuit=$(MODEL) \

9
vlsi/tutorial.mk
View File

@@ -1,7 +1,10 @@
######################################################################################### #########################################################################################
# makefile variables for Hammer tutorials # makefile variables for Hammer tutorials
######################################################################################### #########################################################################################
tutorial ?= none # tutorial ?= none
tutorial ?= sky130-openroad
extra ?=
# TODO: eventually have asap7 commercial/openroad tutorial flavors # TODO: eventually have asap7 commercial/openroad tutorial flavors
ifeq ($(tutorial),asap7) ifeq ($(tutorial),asap7)
@@ -34,5 +37,7 @@ ifeq ($(tutorial),sky130-openroad)
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
VLSI_OBJ_DIR ?= build-sky130-openroad VLSI_OBJ_DIR ?= build-sky130-openroad
# Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.
ENABLE_CUSTOM_FIRRTL_PASS = 1 ENABLE_YOSYS_FLOW = 1
endif endif
HAMMER_EXTRA_ARGS ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)