diff --git a/common.mk b/common.mk index c62743e0..d0526444 100644 --- a/common.mk +++ b/common.mk @@ -18,6 +18,7 @@ HELP_COMPILATION_VARIABLES += \ " EXTRA_SIM_REQS = additional make requirements to build the simulator" \ " ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \ " ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \ +" ENABLE_YOSYS_FLOW = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow) \ " EXTRA_CHISEL_OPTIONS = additional options to pass to the Chisel compiler" \ " EXTRA_FIRRTL_OPTIONS = additional options to pass to the FIRRTL compiler" @@ -26,6 +27,7 @@ EXTRA_SIM_CXXFLAGS ?= EXTRA_SIM_LDFLAGS ?= EXTRA_SIM_SOURCES ?= EXTRA_SIM_REQS ?= +ENABLE_CUSTOM_FIRRTL_PASS += $(ENABLE_YOSYS_FLOW) #---------------------------------------------------------------------------- HELP_SIMULATION_VARIABLES += \ @@ -159,6 +161,7 @@ SFC_MFC_TARGETS = \ $(GEN_COLLATERAL_DIR) SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) +MFC_BASE_LOWERING_OPTIONS = emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket # DOC include start: FirrtlCompiler # There are two possible cases for this step. In the first case, SFC @@ -171,13 +174,18 @@ SFC_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SFC_SMEMS_CONF) # hack: lower to low firrtl if Fixed types are found # hack: when using dontTouch, io.cpu annotations are not removed by SFC, # hence we remove them manually by using jq before passing them to firtool -$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) +$(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS) $(FINAL_ANNO_FILE) $(MFC_LOWERING_OPTIONS) &: $(FIRRTL_FILE) $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) ifeq (,$(ENABLE_CUSTOM_FIRRTL_PASS)) $(eval SFC_LEVEL := $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), low, none)) $(eval EXTRA_FIRRTL_OPTIONS += $(if $(shell grep "Fixed<" $(FIRRTL_FILE)), $(SFC_REPL_SEQ_MEM),)) else $(eval SFC_LEVEL := low) $(eval EXTRA_FIRRTL_OPTIONS += $(SFC_REPL_SEQ_MEM)) +endif +ifeq (,$(ENABLE_YOSYS_FLOW)) + $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS)) +else + $(eval MFC_LOWERING_OPTIONS = $(MFC_BASE_LOWERING_OPTIONS),disallowPackedArrays) endif if [ $(SFC_LEVEL) = low ]; then jq -s '[.[][]]' $(EXTRA_ANNO_FILE) $(SFC_EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi @@ -210,7 +218,7 @@ $(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(VLOG_SOURCES) $(SFC_LE --disable-annotation-classless \ --disable-annotation-unknown \ --mlir-timing \ - --lowering-options=emittedLineLength=2048,noAlwaysComb,disallowLocalVariables,verifLabels,locationInfoStyle=wrapInAtSquareBracket \ + --lowering-options=$(MFC_LOWERING_OPTIONS) \ --repl-seq-mem \ --repl-seq-mem-file=$(MFC_SMEMS_CONF) \ --repl-seq-mem-circuit=$(MODEL) \ diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk index 9b69b149..b3d88741 100644 --- a/vlsi/tutorial.mk +++ b/vlsi/tutorial.mk @@ -1,7 +1,10 @@ ######################################################################################### # makefile variables for Hammer tutorials ######################################################################################### -tutorial ?= none +# tutorial ?= none +tutorial ?= sky130-openroad + +extra ?= # TODO: eventually have asap7 commercial/openroad tutorial flavors ifeq ($(tutorial),asap7) @@ -34,5 +37,7 @@ ifeq ($(tutorial),sky130-openroad) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS) VLSI_OBJ_DIR ?= build-sky130-openroad # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time. - ENABLE_CUSTOM_FIRRTL_PASS = 1 + ENABLE_YOSYS_FLOW = 1 endif + +HAMMER_EXTRA_ARGS ?= -p $(TOOLS_CONF) -p $(TECH_CONF) -p $(DESIGN_CONF) $(extra)