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Merge pull request #1278 from Lorilandly/vc707fpga

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Add support for VC707 FPGA board changelog:added
This commit is contained in:
Abraham Gonzalez
2022-12-14 19:16:49 -08:00
committed by GitHub
parent cb56f8f8f9 5c55614115
commit 8e851b0285
13 changed files with 378 additions and 51 deletions
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7
fpga/src/main/scala/arty/Configs.scala
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@@ -26,6 +26,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
debugIdleCycles = 5)
case SerialTLKey => None // remove serialized tl port
})
// DOC include start: AbstractArty and Rocket
class WithArtyTweaks extends Config(
new WithArtyJTAGHarnessBinder ++
@@ -33,9 +34,11 @@ class WithArtyTweaks extends Config(
new WithArtyResetHarnessBinder ++
new WithDebugResetPassthrough ++
new WithDefaultPeripherals ++
new freechips.rocketchip.subsystem.WithNBreakpoints(2))
new freechips.rocketchip.subsystem.WithNBreakpoints(2)
)
class TinyRocketArtyConfig extends Config(
new WithArtyTweaks ++
new chipyard.TinyRocketConfig)
new chipyard.TinyRocketConfig
)
// DOC include end: AbstractArty and Rocket

58
fpga/src/main/scala/arty/HarnessBinders.scala
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@@ -2,13 +2,12 @@ package chipyard.fpga.arty
import chisel3._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.jtag.{JTAGIO}
import freechips.rocketchip.subsystem._
import sifive.blocks.devices.uart._
import sifive.blocks.devices.jtag._
import sifive.blocks.devices.pinctrl._
import sifive.blocks.devices.uart.{UARTPortIO, HasPeripheryUARTModuleImp}
import sifive.blocks.devices.jtag.{JTAGPins, JTAGPinsFromPort}
import sifive.blocks.devices.pinctrl.{BasePin}
import sifive.fpgashells.ip.xilinx.{IBUFG, IOBUF, PULLUP, PowerOnResetFPGAOnly}
@@ -32,39 +31,38 @@ class WithArtyResetHarnessBinder extends ComposeHarnessBinder({
class WithArtyJTAGHarnessBinder extends OverrideHarnessBinder({
(system: HasPeripheryDebug, th: ArtyFPGATestHarness, ports: Seq[Data]) => {
ports.map {
case j: JTAGChipIO =>
withClockAndReset(th.buildtopClock, th.hReset) {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := j.TDO
jtag_wire.TDO.driven := true.B
j.TCK := jtag_wire.TCK
j.TMS := jtag_wire.TMS
j.TDI := jtag_wire.TDI
case j: JTAGChipIO => withClockAndReset(th.buildtopClock, th.hReset) {
val jtag_wire = Wire(new JTAGIO)
jtag_wire.TDO.data := j.TDO
jtag_wire.TDO.driven := true.B
j.TCK := jtag_wire.TCK
j.TMS := jtag_wire.TMS
j.TDI := jtag_wire.TDI
val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
val io_jtag = Wire(new JTAGPins(() => new BasePin(), false)).suggestName("jtag")
JTAGPinsFromPort(io_jtag, jtag_wire)
JTAGPinsFromPort(io_jtag, jtag_wire)
io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
io_jtag.TCK.i.ival := IBUFG(IOBUF(th.jd_2).asClock).asBool
IOBUF(th.jd_5, io_jtag.TMS)
PULLUP(th.jd_5)
IOBUF(th.jd_5, io_jtag.TMS)
PULLUP(th.jd_5)
IOBUF(th.jd_4, io_jtag.TDI)
PULLUP(th.jd_4)
IOBUF(th.jd_4, io_jtag.TDI)
PULLUP(th.jd_4)
IOBUF(th.jd_0, io_jtag.TDO)
IOBUF(th.jd_0, io_jtag.TDO)
// mimic putting a pullup on this line (part of reset vote)
th.SRST_n := IOBUF(th.jd_6)
PULLUP(th.jd_6)
// mimic putting a pullup on this line (part of reset vote)
th.SRST_n := IOBUF(th.jd_6)
PULLUP(th.jd_6)
// ignore the po input
io_jtag.TCK.i.po.map(_ := DontCare)
io_jtag.TDI.i.po.map(_ := DontCare)
io_jtag.TMS.i.po.map(_ := DontCare)
io_jtag.TDO.i.po.map(_ := DontCare)
}
// ignore the po input
io_jtag.TCK.i.po.map(_ := DontCare)
io_jtag.TDI.i.po.map(_ := DontCare)
io_jtag.TMS.i.po.map(_ := DontCare)
io_jtag.TDO.i.po.map(_ := DontCare)
}
}
}
})

3
fpga/src/main/scala/arty/IOBinders.scala
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@@ -3,8 +3,7 @@ package chipyard.fpga.arty
import chisel3._
import chisel3.experimental.{IO}
import freechips.rocketchip.util._
import freechips.rocketchip.devices.debug._
import freechips.rocketchip.devices.debug.{HasPeripheryDebugModuleImp}
import chipyard.iobinders.{ComposeIOBinder}