45 lines
1.3 KiB
Scala
45 lines
1.3 KiB
Scala
// See LICENSE for license details.
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package chipyard.fpga.arty
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.uart._
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import testchipip.{SerialTLKey}
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import chipyard.{BuildSystem}
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class WithDefaultPeripherals extends Config((site, here, up) => {
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case PeripheryUARTKey => List(
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UARTParams(address = 0x10013000))
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case DTSTimebase => BigInt(32768)
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case JtagDTMKey => new JtagDTMConfig (
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idcodeVersion = 2,
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idcodePartNum = 0x000,
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idcodeManufId = 0x489,
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debugIdleCycles = 5)
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case SerialTLKey => None // remove serialized tl port
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})
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// DOC include start: AbstractArty and Rocket
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class WithArtyTweaks extends Config(
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new WithArtyJTAGHarnessBinder ++
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new WithArtyUARTHarnessBinder ++
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new WithArtyResetHarnessBinder ++
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new WithDebugResetPassthrough ++
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new WithDefaultPeripherals ++
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new freechips.rocketchip.subsystem.WithNBreakpoints(2)
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)
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class TinyRocketArtyConfig extends Config(
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new WithArtyTweaks ++
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new chipyard.TinyRocketConfig
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)
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// DOC include end: AbstractArty and Rocket
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