wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Support multi-TSI/multi-SimDRAM

Browse Source
This commit is contained in:
Jerry Zhao
2023-12-26 12:52:23 -08:00
parent 81cc556c3b
commit 8e37dcdf81
2 changed files with 11 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
generators/chipyard/src/main/scala/config/ChipletConfigs.scala
View File

@@ -36,3 +36,11 @@ class SymmetricChipletRocketConfig extends Config(
new testchipip.soc.WithOffchipBus ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// Simulates 2X of the SymmetricChipletRocketConfig in a multi-sim config
class MultiSimSymmetricChipletRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=1) ++
new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
)

8
generators/chipyard/src/main/scala/harness/HarnessBinders.scala
View File

@@ -50,9 +50,7 @@ class WithGPIOTiedOff extends HarnessBinder({
class WithUARTAdapter extends HarnessBinder({
case (th: HasHarnessInstantiators, port: UARTPort) => {
val div = (th.getHarnessBinderClockFreqMHz.toDouble * 1000000 / port.io.c.initBaudRate.toDouble).toInt
val uart_sim = Module(new UARTAdapter(port.uartNo, div, false)).suggestName(s"uart_sim_uartno${port.uartNo}")
uart_sim.io.uart.txd := port.io.txd
port.io.rxd := uart_sim.io.uart.rxd
UARTAdapter.connect(Seq(port.io), div, false)
}
})
// DOC include end: WithUARTAdapter
@@ -113,7 +111,7 @@ class WithBlackBoxSimMem(additionalLatency: Int = 0) extends HarnessBinder({
val memBase = port.params.master.base
val lineSize = 64 // cache block size
val clockFreq = port.clockFreqMHz
val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle)).suggestName("simdram")
val mem = Module(new SimDRAM(memSize, lineSize, clockFreq, memBase, port.edge.bundle, th.p(MultiChipIdx))).suggestName("simdram")
mem.io.clock := port.io.clock
mem.io.reset := th.harnessBinderReset.asAsyncReset
@@ -246,7 +244,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
ram.io.ser.in <> io.out
io.in <> ram.io.ser.out
val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset)
val success = SimTSI.connect(ram.io.tsi, clock, th.harnessBinderReset, th.p(MultiChipIdx))
when (success) { th.success := true.B }
}
}