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vlsi: Add make_syn_f.sh to VLSI_RTL target

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This script appends Vortex verilog sources & reorders compilation order to
synthesis input config.
This commit is contained in:
Hansung Kim
2024-07-30 08:03:53 -07:00
parent 845679b9fe
commit 8b9fee03bb
1 changed files with 1 additions and 0 deletions
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vlsi/Makefile
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@@ -87,6 +87,7 @@ ifneq ($(EXT_FILELISTS),)
cat $(EXT_FILELISTS) >> $(VLSI_RTL) cat $(EXT_FILELISTS) >> $(VLSI_RTL)
endif endif
endif endif
$(vlsi_dir)/make_syn_f.sh $(build_dir)
######################################################################################### #########################################################################################
# srams # srams