From 8b9fee03bb41e80755379910c883cccef6f51ee1 Mon Sep 17 00:00:00 2001 From: Hansung Kim Date: Tue, 30 Jul 2024 08:03:53 -0700 Subject: [PATCH] vlsi: Add make_syn_f.sh to VLSI_RTL target This script appends Vortex verilog sources & reorders compilation order to synthesis input config. --- vlsi/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/vlsi/Makefile b/vlsi/Makefile index 939d473f..b7b56ee5 100644 --- a/vlsi/Makefile +++ b/vlsi/Makefile @@ -87,6 +87,7 @@ ifneq ($(EXT_FILELISTS),) cat $(EXT_FILELISTS) >> $(VLSI_RTL) endif endif + $(vlsi_dir)/make_syn_f.sh $(build_dir) ######################################################################################### # srams