first attempt at heter. port
This commit is contained in:
abejgonzalez
@@ -0,0 +1,94 @@
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package example
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import chisel3._
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import chisel3.internal.sourceinfo.{SourceInfo}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import boom.system.{BoomTilesKey}
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trait HasBoomAndRocketTiles extends HasTiles
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with CanHavePeripheryPLIC
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with CanHavePeripheryCLINT
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with HasPeripheryDebug
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{ this: BaseSubsystem =>
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val module: HasBoomAndRocketTilesModuleImp
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protected val rocketTileParams = p(RocketTilesKey)
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protected val boomTileParams = p(BoomTilesKey)
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private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
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private val boomCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), boomTileParams.size)
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// Make a tile and wire its nodes into the system,
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// according to the specified type of clock crossing.
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// Note that we also inject new nodes into the tile itself,
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// also based on the crossing type.
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val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
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val rocket = LazyModule(new RocketTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name)
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connectMasterPortsToSBus(rocket, crossing)
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connectSlavePortsToCBus(rocket, crossing)
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connectInterrupts(rocket, Some(debug), clintOpt, plicOpt)
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rocket
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}
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println(s"DEBUG: Amount of rocket tiles: ${rocketTiles.length}")
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val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
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val boomCore = LazyModule(
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new boom.common.BoomTile(tp, crossing.crossingType)(augmentedTileParameters(tp))).suggestName(tp.name)
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connectMasterPortsToSBus(boomCore, crossing)
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connectSlavePortsToCBus(boomCore, crossing)
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connectInterrupts(boomCore, Some(debug), clintOpt, plicOpt)
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boomCore
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}
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println(s"DEBUG: Amount of boom tiles: ${boomTiles.length}")
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val boomAndRocketTiles = rocketTiles ++ boomTiles
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println(s"DEBUG: Amount of both tiles: ${boomAndRocketTiles.length}")
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def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
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(boomTiles map { t => t.module.core.coreMonitorBundle}).toList
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def getOMRocketInterruptTargets(): Seq[OMInterruptTarget] =
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boomAndRocketTiles.flatMap(c => c.cpuDevice.getInterruptTargets())
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def getOMRocketCores(resourceBindingsMap: ResourceBindingsMap): Seq[OMComponent] =
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boomAndRocketTiles.flatMap(c => c.cpuDevice.getOMComponents(resourceBindingsMap))
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}
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trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
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with HasPeripheryDebugModuleImp {
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val outer: HasBoomAndRocketTiles
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}
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class BoomAndRocketSubsystem(implicit p: Parameters) extends BaseSubsystem
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with HasBoomAndRocketTiles {
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val tiles = boomAndRocketTiles
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override lazy val module = new BoomAndRocketSubsystemModuleImp(this)
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}
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class BoomAndRocketSubsystemModuleImp[+L <: BoomAndRocketSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
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with HasBoomAndRocketTilesModuleImp {
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tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
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wire.clock := clock
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wire.reset := reset
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wire.hartid := i.U
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wire.reset_vector := global_reset_vector
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}
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}
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@@ -168,3 +168,69 @@ class WithGPIOBoomTop extends Config((site, here, up) => {
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top
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}
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})
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// --------------------------------------
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// BOOM + Rocket Top Level System Parameter Mixins
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// --------------------------------------
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/**
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* Class to specify a "plain" top level BOOM + Rocket system
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*/
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class WithNormalBoomAndRocketTop extends Config((site, here, up) => {
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case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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Module(LazyModule(new BoomAndRocketTop()(p)).module)
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}
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})
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/**
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* Class to specify a top level BOOM + Rocket system with PWM
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*/
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class WithPWMBoomAndRocketTop extends Config((site, here, up) => {
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case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new BoomAndRocketTopWithPWMTL()(p)).module)
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})
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/**
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* Class to specify a top level BOOM + Rocket system with a PWM AXI4
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*/
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class WithPWMAXI4BoomAndRocketTop extends Config((site, here, up) => {
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case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
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Module(LazyModule(new BoomAndRocketTopWithPWMAXI4()(p)).module)
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})
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/**
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* Class to specify a top level BOOM + Rocket system with a block device
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*/
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class WithBlockDeviceModelBoomAndRocketTop extends Config((site, here, up) => {
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case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module)
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top.connectBlockDeviceModel()
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top
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}
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})
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/**
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* Class to specify a top level BOOM + Rocket system with a simulator block device
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*/
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class WithSimBlockDeviceBoomAndRocketTop extends Config((site, here, up) => {
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case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomAndRocketTopWithBlockDevice()(p)).module)
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top.connectSimBlockDevice(clock, reset)
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top
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}
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})
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/**
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* Class to specify a top level BOOM + Rocket system with GPIO
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*/
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class WithGPIOBoomAndRocketTop extends Config((site, here, up) => {
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case BuildBoomAndRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
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val top = Module(LazyModule(new BoomAndRocketTopWithGPIO()(p)).module)
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for (gpio <- top.gpio) {
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for (pin <- gpio.pins) {
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pin.i.ival := false.B
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}
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}
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top
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}
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})
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@@ -106,10 +106,28 @@ class BlockDeviceModelBoomConfig extends Config(
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new WithBlockDeviceModelBoomTop ++
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new BaseBoomConfig)
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/**
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* Slightly different looking configs since we need to override
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* the `WithNBoomCores` with the DefaultBoomConfig params
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*/
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class DualCoreBoomConfig extends Config(
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// Core gets tacked onto existing list
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new WithNormalBoomTop ++
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new WithBootROM ++
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new boom.common.WithRVC ++
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new boom.common.DefaultBoomConfig ++
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new boom.system.WithNBoomCores(2) ++
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new DefaultBoomConfig)
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.system.BaseConfig)
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class DualCoreSmallBoomConfig extends Config(
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new WithNormalBoomTop ++
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new WithBootROM ++
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new boom.common.WithRVC ++
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new boom.common.WithSmallBooms ++
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new boom.common.DefaultBoomConfig ++
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new boom.system.WithNBoomCores(2) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.system.BaseConfig)
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class RV32BoomConfig extends Config(
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new WithBootROM ++
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@@ -119,3 +137,101 @@ class GPIOBoomConfig extends Config(
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new WithGPIO ++
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new WithGPIOBoomTop ++
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new BaseBoomConfig)
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// ---------------------
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// BOOM + Rocket Configs
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// ---------------------
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//class BaseRocketConfig extends Config(
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// new WithBootROM ++
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// new freechips.rocketchip.system.DefaultConfig)
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//
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//class DefaultRocketConfig extends Config(
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// new WithNormalRocketTop ++
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// new BaseRocketConfig)
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//
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//class BaseConfig extends Config(
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// new WithDefaultMemPort() ++
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// new WithDefaultMMIOPort() ++
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// new WithDefaultSlavePort() ++
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// new WithTimebase(BigInt(1000000)) ++ // 1 MHz
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// new WithDTS("freechips,rocketchip-unknown", Nil) ++
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// new WithNExtTopInterrupts(2) ++
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// new BaseSubsystemConfig()
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//)
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//
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//class DefaultConfig extends Config(new WithNBigCores(1) ++ new BaseConfig)
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//
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////boom
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// new WithRVC ++
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// new DefaultBoomConfig ++
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// new WithNBoomCores(1) ++
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// new WithoutTLMonitors ++
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// new freechips.rocketchip.system.BaseConfig)
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class BaseBoomAndRocketConfig extends Config(
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new WithBootROM ++
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new boom.common.WithRVC ++
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new boom.common.DefaultBoomConfig ++
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new boom.system.WithNBoomCores(1) ++
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new freechips.rocketchip.subsystem.WithoutTLMonitors ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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//class BaseBoomAndRocketConfig extends Config(
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// new WithBootROM ++
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// new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// new boom.system.BoomConfig)
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class SmallBaseBoomAndRocketConfig extends Config(
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new WithBootROM ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new boom.system.SmallBoomConfig)
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class DefaultBoomAndRocketConfig extends Config(
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new WithNormalBoomAndRocketTop ++
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new BaseBoomAndRocketConfig)
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class SmallDefaultBoomAndRocketConfig extends Config(
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new WithNormalBoomAndRocketTop ++
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new SmallBaseBoomAndRocketConfig)
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class HwachaBoomAndRocketConfig extends Config(
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new hwacha.DefaultHwachaConfig ++
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new DefaultBoomAndRocketConfig)
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class RoccBoomAndRocketConfig extends Config(
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new WithRoccExample ++
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new DefaultBoomAndRocketConfig)
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class PWMBoomAndRocketConfig extends Config(
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new WithPWMBoomAndRocketTop ++
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new BaseBoomAndRocketConfig)
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class PWMAXI4BoomAndRocketConfig extends Config(
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new WithPWMAXI4BoomAndRocketTop ++
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new BaseBoomAndRocketConfig)
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class SimBlockDeviceBoomAndRocketConfig extends Config(
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new WithBlockDevice ++
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new WithSimBlockDeviceBoomAndRocketTop ++
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new BaseBoomAndRocketConfig)
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class BlockDeviceModelBoomAndRocketConfig extends Config(
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new WithBlockDevice ++
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new WithBlockDeviceModelBoomAndRocketTop ++
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new BaseBoomAndRocketConfig)
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class DualCoreBoomAndOneRocketConfig extends Config(
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// Core gets tacked onto existing list
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new boom.system.WithNBoomCores(2) ++
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new DefaultBoomAndRocketConfig)
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class RV32BoomAndNormalRocketConfig extends Config(
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new WithBootROM ++
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new boom.system.SmallRV32UnifiedBoomConfig)
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class GPIOBoomAndRocketConfig extends Config(
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new WithGPIO ++
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new WithGPIOBoomAndRocketTop ++
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new BaseBoomAndRocketConfig)
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@@ -0,0 +1,62 @@
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package example
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import chisel3._
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import chisel3.internal.sourceinfo.{SourceInfo}
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import freechips.rocketchip.config.{Field, Parameters}
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomaticobjectmodel.model.{OMComponent, OMInterruptTarget}
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import freechips.rocketchip.tile._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.amba.axi4._
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import boom.system.{BoomTilesKey}
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/**
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* Example top with periphery devices and ports, and a BOOM subsystem
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*/
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class ExampleBoomAndRocketSystem(implicit p: Parameters) extends BoomAndRocketSubsystem
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with HasAsyncExtInterrupts
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with boom.system.CanHaveMisalignedMasterAXI4MemPort
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with CanHaveMasterAXI4MMIOPort
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with CanHaveSlaveAXI4Port
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with HasPeripheryBootROM
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{
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override lazy val module = new ExampleBoomAndRocketSystemModule(this)
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// The sbus masters the cbus; here we convert TL-UH -> TL-UL
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sbus.crossToBus(cbus, NoCrossing)
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// The cbus masters the pbus; which might be clocked slower
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cbus.crossToBus(pbus, SynchronousCrossing())
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// The fbus masters the sbus; both are TL-UH or TL-C
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FlipRendering { implicit p =>
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sbus.crossFromBus(fbus, SynchronousCrossing())
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}
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// The sbus masters the mbus; here we convert TL-C -> TL-UH
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private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key)
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private val (in, out, halt) = coherenceManager(this)
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if (nBanks != 0) {
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sbus.coupleTo("coherence_manager") { in :*= _ }
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mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out }
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}
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}
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/**
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* Example top module with periphery devices and ports, and a BOOM subsystem
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*/
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class ExampleBoomAndRocketSystemModule[+L <: ExampleBoomAndRocketSystem](_outer: L) extends BoomAndRocketSubsystemModuleImp(_outer)
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with HasRTCModuleImp
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with HasExtInterruptsModuleImp
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with boom.system.CanHaveMisalignedMasterAXI4MemPortModuleImp
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with CanHaveMasterAXI4MMIOPortModuleImp
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with CanHaveSlaveAXI4PortModuleImp
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with HasPeripheryBootROMModuleImp
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with DontTouch
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@@ -77,3 +77,38 @@ class BoomTestHarness(implicit val p: Parameters) extends Module {
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})
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io.success := dut.connectSimSerial()
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}
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// --------------------------
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// BOOM + Rocket Test Harness
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// --------------------------
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case object BuildBoomAndRocketTop extends Field[(Clock, Bool, Parameters) => BoomAndRocketTopModule[BoomAndRocketTop]]
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class BoomAndRocketTestHarness(implicit val p: Parameters) extends Module {
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val io = IO(new Bundle {
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val success = Output(Bool())
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})
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// force Chisel to rename module
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override def desiredName = "TestHarness"
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val dut = p(BuildBoomAndRocketTop)(clock, reset.toBool, p)
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dut.debug := DontCare
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dut.connectSimAXIMem()
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dut.connectSimAXIMMIO()
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dut.dontTouchPorts()
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dut.tieOffInterrupts()
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dut.l2_frontend_bus_axi4.foreach(axi => {
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axi.tieoff()
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experimental.DataMirror.directionOf(axi.ar.ready) match {
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case core.ActualDirection.Input =>
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axi.r.bits := DontCare
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axi.b.bits := DontCare
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case core.ActualDirection.Output =>
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axi.aw.bits := DontCare
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axi.ar.bits := DontCare
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axi.w.bits := DontCare
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}
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})
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io.success := dut.connectSimSerial()
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}
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@@ -127,3 +127,60 @@ class BoomTopWithGPIO(implicit p: Parameters) extends BoomTop
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class BoomTopWithGPIOModule(l: BoomTopWithGPIO)
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extends BoomTopModule(l)
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with HasPeripheryGPIOModuleImp
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// -------------------------------
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// BOOM + Rocket Top Level Systems
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// -------------------------------
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class BoomAndRocketTop(implicit p: Parameters) extends ExampleBoomAndRocketSystem
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with HasNoDebug
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with HasPeripherySerial {
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override lazy val module = new BoomAndRocketTopModule(this)
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}
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class BoomAndRocketTopModule[+L <: BoomAndRocketTop](l: L) extends ExampleBoomAndRocketSystemModule(l)
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with HasRTCModuleImp
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with HasNoDebugModuleImp
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with HasPeripherySerialModuleImp
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with DontTouch
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//---------------------------------------------------------------------------------------------------------
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class BoomAndRocketTopWithPWMTL(implicit p: Parameters) extends BoomAndRocketTop
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with HasPeripheryPWMTL {
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override lazy val module = new BoomAndRocketTopWithPWMTLModule(this)
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}
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class BoomAndRocketTopWithPWMTLModule(l: BoomAndRocketTopWithPWMTL) extends BoomAndRocketTopModule(l)
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with HasPeripheryPWMTLModuleImp
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//---------------------------------------------------------------------------------------------------------
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class BoomAndRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomAndRocketTop
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with HasPeripheryPWMAXI4 {
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override lazy val module = new BoomAndRocketTopWithPWMAXI4Module(this)
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}
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class BoomAndRocketTopWithPWMAXI4Module(l: BoomAndRocketTopWithPWMAXI4) extends BoomAndRocketTopModule(l)
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with HasPeripheryPWMAXI4ModuleImp
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//---------------------------------------------------------------------------------------------------------
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class BoomAndRocketTopWithBlockDevice(implicit p: Parameters) extends BoomAndRocketTop
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with HasPeripheryBlockDevice {
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override lazy val module = new BoomAndRocketTopWithBlockDeviceModule(this)
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}
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|
||||
class BoomAndRocketTopWithBlockDeviceModule(l: BoomAndRocketTopWithBlockDevice) extends BoomAndRocketTopModule(l)
|
||||
with HasPeripheryBlockDeviceModuleImp
|
||||
|
||||
//---------------------------------------------------------------------------------------------------------
|
||||
|
||||
class BoomAndRocketTopWithGPIO(implicit p: Parameters) extends BoomAndRocketTop
|
||||
with HasPeripheryGPIO {
|
||||
override lazy val module = new BoomAndRocketTopWithGPIOModule(this)
|
||||
}
|
||||
|
||||
class BoomAndRocketTopWithGPIOModule(l: BoomAndRocketTopWithGPIO)
|
||||
extends BoomAndRocketTopModule(l)
|
||||
with HasPeripheryGPIOModuleImp
|
||||
|
||||
12
variables.mk
12
variables.mk
@@ -50,6 +50,18 @@ ifeq ($(SUB_PROJECT),boomexample)
|
||||
TB ?= TestDriver
|
||||
TOP ?= BoomTop
|
||||
endif
|
||||
# for a BOOM + Rocket based example system
|
||||
ifeq ($(SUB_PROJECT),boomrocketexample)
|
||||
SBT_PROJECT ?= example
|
||||
MODEL ?= BoomAndRocketTestHarness
|
||||
VLOG_MODEL ?= TestHarness
|
||||
MODEL_PACKAGE ?= $(SBT_PROJECT)
|
||||
CONFIG ?= DefaultBoomAndRocketConfig
|
||||
CONFIG_PACKAGE ?= $(SBT_PROJECT)
|
||||
GENERATOR_PACKAGE ?= $(SBT_PROJECT)
|
||||
TB ?= TestDriver
|
||||
TOP ?= BoomAndRocketTop
|
||||
endif
|
||||
# for BOOM developers
|
||||
ifeq ($(SUB_PROJECT),boom)
|
||||
SBT_PROJECT ?= boom
|
||||
|
||||
Reference in New Issue
Block a user