Merge pull request #145 from ucb-bar/filter-c-files

Stop *.h pollution | BlockDev CI
2019-07-17 15:21:33 -07:00
parent a1fb95c037 56b5cea816
commit 8ac26852b4
14 changed files with 120 additions and 106 deletions
--- a/.circleci/config.yml
+++ b/.circleci/config.yml
@@ -233,6 +233,35 @@ jobs:
                key: rocketchip-{{ .Branch }}-{{ .Revision }}
                paths:
                    - "/home/riscvuser/project"
+    prepare-blockdevrocketchip:
+        docker:
+            - image: riscvboom/riscvboom-images:0.0.10
+        environment:
+            JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
+            TERM: dumb
+        steps:
+            - add_ssh_keys:
+                fingerprints:
+                    - "3e:c3:02:5b:ed:64:8c:b7:b0:04:43:bc:83:43:73:1e"
+            - checkout
+            - run:
+                name: Create hash of toolchains
+                command: |
+                    .circleci/create-hash.sh
+            - restore_cache:
+                keys:
+                    - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
+            - restore_cache:
+                keys:
+                    - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
+            - run:
+                name: Building the blockdevrocketchip subproject using Verilator
+                command: .circleci/do-rtl-build.sh blockdevrocketchip
+                no_output_timeout: 120m
+            - save_cache:
+                key: blockdevrocketchip-{{ .Branch }}-{{ .Revision }}
+                paths:
+                    - "/home/riscvuser/project"
    prepare-hwacha:
        docker:
            - image: riscvboom/riscvboom-images:0.0.10
@@ -449,6 +478,11 @@ workflows:
                    - install-riscv-toolchain
                    - install-verilator

+            - prepare-blockdevrocketchip:
+                requires:
+                    - install-riscv-toolchain
+                    - install-verilator
+
            - prepare-hwacha:
                requires:
                    - install-esp-toolchain
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -40,4 +40,5 @@ mapping["boomexample"]="SUB_PROJECT=example CONFIG=DefaultBoomConfig"
 mapping["boomrocketexample"]="SUB_PROJECT=example CONFIG=DefaultBoomAndRocketConfig"
 mapping["boom"]="SUB_PROJECT=boom"
 mapping["rocketchip"]="SUB_PROJECT=rocketchip"
+mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=BlockDeviceModelRocketConfig TOP=BoomRocketTopWithBlockDevice"
 mapping["hwacha"]="SUB_PROJECT=hwacha"
--- a/.circleci/do-rtl-build.sh
+++ b/.circleci/do-rtl-build.sh
@@ -39,7 +39,7 @@ else
    copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
 fi

-# enter the verisim directory and build the specific config on remote server
+# enter the verilator directory and build the specific config on remote server
 run "make -C $REMOTE_SIM_DIR clean"
 run "export RISCV=\"$TOOLS_DIR\"; export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; export VERILATOR_ROOT=$REMOTE_VERILATOR_DIR/install/share/verilator; make -C $REMOTE_SIM_DIR VERILATOR_INSTALL_DIR=$REMOTE_VERILATOR_DIR JAVA_ARGS=\"-Xmx8G -Xss8M\" ${mapping[$1]}"
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
--- a/common.mk
+++ b/common.mk
@@ -33,39 +33,46 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(CHIPYARD_FIRRTL_DIR)/src/main/scala)
 #########################################################################################
 # create simulation args file rule
 #########################################################################################
-$(sim_dotf): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR)
+$(sim_files): $(call lookup_scala_srcs,$(base_dir)/generators/utilities/src/main/scala) $(FIRRTL_JAR)
 	cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"

 #########################################################################################
 # create firrtl file rule and variables
 #########################################################################################
-$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_dotf)
+$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(sim_files)
 	mkdir -p $(build_dir)
 	cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator $(build_dir) $(MODEL_PACKAGE) $(MODEL) $(CONFIG_PACKAGE) $(CONFIG)"

 #########################################################################################
 # create verilog files rules and variables
 #########################################################################################
-REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(SMEMS_CONF)
+REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(TOP_SMEMS_CONF)
 HARNESS_REPL_SEQ_MEM = --infer-rw --repl-seq-mem -c:$(MODEL):-o:$(HARNESS_SMEMS_CONF)

-$(VERILOG_FILE) $(SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
-	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(VERILOG_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
-	cp $(build_dir)/firrtl_black_box_resource_files.f $(sim_top_blackboxes)
+$(TOP_FILE) $(TOP_SMEMS_CONF) $(TOP_ANNO) $(TOP_FIR) $(sim_top_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE)
+	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTop -o $(TOP_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tsf $(TOP_FIR) $(REPL_SEQ_MEM) -td $(build_dir)"
+	grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_top_blackboxes)

-$(HARNESS_FILE) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
+# note: this depends on sim_top_blackboxes to avoid race condition where firrtl_black_box_resource_files.f is created at the same time
+$(HARNESS_FILE) $(HARNESS_SMEMS_CONF) $(HARNESS_ANNO) $(HARNESS_FIR) $(sim_harness_blackboxes): $(FIRRTL_FILE) $(ANNO_FILE) $(sim_top_blackboxes)
 	cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateHarness -o $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -thaof $(HARNESS_ANNO) -thf $(HARNESS_FIR) $(HARNESS_REPL_SEQ_MEM) -td $(build_dir)"
-	grep -v ".*\.cc" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)
+	grep -v ".*\.h" $(build_dir)/firrtl_black_box_resource_files.f > $(sim_harness_blackboxes)

 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 MACROCOMPILER_MODE ?= --mode synflops
-$(SMEMS_FILE) $(SMEMS_FIR): $(SMEMS_CONF)
-	cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(SMEMS_CONF) -v $(SMEMS_FILE) -f $(SMEMS_FIR) $(MACROCOMPILER_MODE)"
+$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): $(TOP_SMEMS_CONF)
+	cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)"

 HARNESS_MACROCOMPILER_MODE = --mode synflops
 $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): $(HARNESS_SMEMS_CONF)
 	cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)"

+########################################################################################
+# remove duplicate files in blackbox/simfiles
+########################################################################################
+$(sim_common_files): $(sim_top_blackboxes) $(sim_harness_blackboxes) $(sim_files)
+	awk '{print $1;}' $^ | sort -u > $@
+
 #########################################################################################
 # helper rule to just make verilog files
 #########################################################################################
--- a/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst
+++ b/docs/Getting-Started/Adding-An-Accelerator-Tutorial.rst
@@ -227,7 +227,7 @@ Now with all of that done, we can go ahead and run our simulation.

 .. code-block:: shell

-    cd verisim
+    cd verilator
    make CONFIG=PWMConfig
    ./simulator-example-PWMConfig ../tests/pwm.riscv

--- a/docs/Getting-Started/Chipyard-Basics.rst
+++ b/docs/Getting-Started/Chipyard-Basics.rst
@@ -81,14 +81,14 @@ Toolchains
 Sims
 -------------------------------------------

-**verisim (Verilator wrapper)**
+**verilator (Verilator wrapper)**
  Verilator is an open source Verilog simulator.
-  The ``verisim`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
+  The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files).
  See :ref:`Verilator` for more information.

-**vsim (VCS wrapper)**
+**vcs (VCS wrapper)**
  VCS is a proprietary Verilog simulator.
-  Assuming the user has valid VCS licenses and installations, the ``vsim`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
+  Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files).
  See :ref:`VCS` for more information.

 **FireSim**
--- a/docs/Getting-Started/Running-A-Simulation.rst
+++ b/docs/Getting-Started/Running-A-Simulation.rst
@@ -15,9 +15,9 @@ The following instructions assume at least one of these simulators is installed.
 Verilator/VCS Flows
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 Verilator is an open-source RTL simulator.
-We run Verilator simulations from within the ``sims/verisim`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
+We run Verilator simulations from within the ``sims/verilator`` directory which provides the necessary ``Makefile`` to both install and run Verilator simulations.
 On the other hand, VCS is a proprietary RTL simulator.
-We run VCS simulations from within the ``sims/vsim`` directory.
+We run VCS simulations from within the ``sims/vcs`` directory.
 Assuming VCS is already installed on the machine running simulations (and is found on our ``PATH``), then this guide is the same for both Verilator and VCS.

 First, we will start by entering the Verilator or VCS directory:
@@ -25,12 +25,12 @@ First, we will start by entering the Verilator or VCS directory:
 .. code-block:: shell

    # Enter Verilator directory
-    cd sims/verisim
+    cd sims/verilator

    # OR

    # Enter VCS directory
-    cd sims/vsim
+    cd sims/vcs

 In order to construct the simulator with our custom design, we run the following command within the simulator directory:

--- a/docs/Simulation/Software-RTL-Simulators.rst
+++ b/docs/Simulation/Software-RTL-Simulators.rst
@@ -9,7 +9,7 @@ The Chipyard framework can download, build, and execute simulations using Verila

 To run a simulation using Verilator, perform the following steps:

-To compile the example design, run ``make`` in the ``sims/verisim`` directory.
+To compile the example design, run ``make`` in the ``sims/verilator`` directory.
 This will elaborate the ``DefaultRocketConfig`` in the example project.

 An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
@@ -47,7 +47,7 @@ To run a simulation using VCS, perform the following steps:

 Make sure that the VCS simulator is on your ``PATH``.

-To compile the example design, run make in the ``sims/vsim`` directory.
+To compile the example design, run make in the ``sims/vcs`` directory.
 This will elaborate the ``DefaultRocketConfig`` in the example project.

 An executable called ``simulator-example-DefaultRocketConfig`` will be produced.
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/scripts/regression.sh
+++ b/scripts/regression.sh
@@ -1,31 +0,0 @@
-#!/bin/bash
-
-# NOTE: TEMPORARY UNTIL CI IS ONLINE
-
-# Run by just giving the test to run (run-bmark-tests | run-asm-tests)
-# Runs in vsim and verisim
-
-set -ex
-set -euo pipefail
-
-cd sims/vsim/
-
-make SUB_PROJECT=rocketchip CONFIG=DefaultConfig
-make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1
-make SUB_PROJECT=boom CONFIG=BoomConfig
-make SUB_PROJECT=boom CONFIG=BoomConfig $1
-make SUB_PROJECT=example CONFIG=DefaultRocketConfig
-make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1
-make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig
-make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1
-
-cd ../verisim/
-
-make SUB_PROJECT=rocketchip CONFIG=DefaultConfig
-make SUB_PROJECT=rocketchip CONFIG=DefaultConfig $1
-make SUB_PROJECT=boom CONFIG=BoomConfig
-make SUB_PROJECT=boom CONFIG=BoomConfig $1
-make SUB_PROJECT=example CONFIG=DefaultRocketConfig
-make SUB_PROJECT=example CONFIG=DefaultRocketConfig $1
-make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig
-make SUB_PROJECT=boomexample CONFIG=DefaultBoomConfig $1
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -61,8 +61,7 @@ VCS_NONCC_OPTS = \
 	+v2k \
 	+vcs+lic+wait \
 	+vc+list \
-	-f $(sim_vcs_blackboxes) \
-	-f $(sim_dotf) \
+	-f $(sim_common_files) \
 	-sverilog \
 	+incdir+$(build_dir) \
 	+define+CLOCK_PERIOD=1.0 \
@@ -77,22 +76,14 @@ VCS_NONCC_OPTS = \

 VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS)

-########################################################################################
-# remove duplicate blackboxes
-########################################################################################
-sim_vcs_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.vcs.f
-
-$(sim_vcs_blackboxes): $(sim_top_blackboxes) $(sim_harness_blackboxes)
-	awk '{print $1;}' $^ | sort -u > $@
-
 #########################################################################################
 # vcs simulator rules
 #########################################################################################
-$(sim): $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes)
+$(sim): $(sim_vsrcs) $(sim_common_files)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	-debug_pp

-$(sim_debug) : $(sim_vsrcs) $(sim_dotf) $(sim_vcs_blackboxes)
+$(sim_debug) : $(sim_vsrcs) $(sim_common_files)
 	rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \
 	+define+DEBUG -debug_pp

@@ -107,4 +98,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(gen_dir)/* csrc $(sim_prefix)-* ucli.key vc_hdrs.h
+	rm -rf $(gen_dir) csrc $(sim_prefix)-* ucli.key vc_hdrs.h
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -40,6 +40,31 @@ debug: $(sim_debug)
 include $(base_dir)/common.mk
 include $(sim_dir)/verilator.mk

+#########################################################################################
+# verilator binary and flags
+#########################################################################################
+VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
+
+CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
+LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread
+
+VERILATOR_CC_OPTS = \
+	-O3 \
+	-CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR" \
+	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs" \
+	-LDFLAGS "$(LDFLAGS)"
+
+VERILATOR_NONCC_OPTS = \
+	--top-module $(VLOG_MODEL) \
+	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
+	+define+STOP_COND=\$$c\(\"done_reset\"\) \
+	--assert \
+	--output-split 20000 \
+	$(sim_vsrcs) \
+	-f $(sim_common_files)
+
+VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
+
 #########################################################################################
 # verilator build paths and file names
 #########################################################################################
@@ -55,35 +80,30 @@ model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
 #########################################################################################
 # build makefile fragment that builds the verilator sim rules
 #########################################################################################
-LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L$(sim_dir) -lfesvr -lpthread

-$(model_mk): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
+$(model_mk): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name)
-	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name) \
-	-o $(sim) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header)"
+	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim) -Mdir $(model_dir) -CFLAGS "-include $(model_header)"
 	touch $@

-$(model_mk_debug): $(sim_vsrcs) $(sim_dotf) $(INSTALLED_VERILATOR)
+$(model_mk_debug): $(sim_vsrcs) $(sim_common_files) $(INSTALLED_VERILATOR)
 	rm -rf $(build_dir)/$(long_name)
 	mkdir -p $(build_dir)/$(long_name).debug
-	$(VERILATOR) $(VERILATOR_FLAGS) -Mdir $(build_dir)/$(long_name).debug --trace \
-	-o $(sim_debug) $(sim_vsrcs) -f $(sim_dotf) -f $(sim_top_blackboxes) -f $(sim_harness_blackboxes) -LDFLAGS "$(LDFLAGS)" \
-	-CFLAGS "-I$(build_dir) -include $(build_dir)/$(long_name).plusArgs -include $(model_header_debug)"
+	$(VERILATOR) $(VERILATOR_OPTS) -o $(sim_debug) --trace -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
 	touch $@

 #########################################################################################
 # invoke make to make verilator sim rules
 #########################################################################################
 $(sim): $(model_mk)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name) -f V$(VLOG_MODEL).mk
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk

 $(sim_debug): $(model_mk_debug)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(build_dir)/$(long_name).debug -f V$(VLOG_MODEL).mk
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk

 #########################################################################################
-# create a verisim vpd rule
+# create a verilator vpd rule
 #########################################################################################
 $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 	rm -f $@.vcd && mkfifo $@.vcd
@@ -95,4 +115,4 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(gen_dir)/* $(sim_prefix)-*
+	rm -rf $(gen_dir) $(sim_prefix)-*
--- a/sims/verilator/verilator.mk
+++ b/sims/verilator/verilator.mk
@@ -6,7 +6,7 @@
 # verilator version, binary, and path
 #########################################################################################
 VERILATOR_VERSION      = 4.016
-VERILATOR_INSTALL_DIR ?= verilator
+VERILATOR_INSTALL_DIR ?= verilator_install
 VERILATOR_SRCDIR       = $(VERILATOR_INSTALL_DIR)/src/verilator-$(VERILATOR_VERSION)
 INSTALLED_VERILATOR    = $(abspath $(VERILATOR_INSTALL_DIR)/install/bin/verilator)

@@ -37,15 +37,3 @@ $(VERILATOR_SRCDIR)/configure: $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VE
 $(VERILATOR_INSTALL_DIR)/verilator-$(VERILATOR_VERSION).tar.gz:
 	mkdir -p $(dir $@)
 	wget https://www.veripool.org/ftp/verilator-$(VERILATOR_VERSION).tgz -O $@
-
-#########################################################################################
-# verilator binary and flags
-#########################################################################################
-VERILATOR := $(INSTALLED_VERILATOR) --cc --exe
-CXXFLAGS := $(CXXFLAGS) -O1 -std=c++11 -I$(RISCV)/include -D__STDC_FORMAT_MACROS
-VERILATOR_FLAGS := --top-module $(VLOG_MODEL) \
-	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
-	+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-	--output-split 20000 \
-	-Wno-STMTDLY --x-assign unique \
-	-O3 -CFLAGS "$(CXXFLAGS) -DTEST_HARNESS=V$(VLOG_MODEL) -DVERILATOR"
--- a/variables.mk
+++ b/variables.mk
@@ -108,23 +108,27 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
 	long_name=$(MODEL_PACKAGE).$(CONFIG)
 endif

-FIRRTL_FILE        ?= $(build_dir)/$(long_name).fir
-ANNO_FILE          ?= $(build_dir)/$(long_name).anno.json
-VERILOG_FILE       ?= $(build_dir)/$(long_name).top.v
-TOP_FIR            ?= $(build_dir)/$(long_name).top.fir
-TOP_ANNO           ?= $(build_dir)/$(long_name).top.anno.json
+FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
+ANNO_FILE   ?= $(build_dir)/$(long_name).anno.json
+
+TOP_FILE       ?= $(build_dir)/$(long_name).top.v
+TOP_FIR        ?= $(build_dir)/$(long_name).top.fir
+TOP_ANNO       ?= $(build_dir)/$(long_name).top.anno.json
+TOP_SMEMS_FILE ?= $(build_dir)/$(long_name).top.mems.v
+TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
+TOP_SMEMS_FIR  ?= $(build_dir)/$(long_name).top.mems.fir
+
 HARNESS_FILE       ?= $(build_dir)/$(long_name).harness.v
 HARNESS_FIR        ?= $(build_dir)/$(long_name).harness.fir
 HARNESS_ANNO       ?= $(build_dir)/$(long_name).harness.anno.json
 HARNESS_SMEMS_FILE ?= $(build_dir)/$(long_name).harness.mems.v
 HARNESS_SMEMS_CONF ?= $(build_dir)/$(long_name).harness.mems.conf
 HARNESS_SMEMS_FIR  ?= $(build_dir)/$(long_name).harness.mems.fir
-SMEMS_FILE         ?= $(build_dir)/$(long_name).mems.v
-SMEMS_CONF         ?= $(build_dir)/$(long_name).mems.conf
-SMEMS_FIR          ?= $(build_dir)/$(long_name).mems.fir
-sim_dotf               ?= $(build_dir)/sim_files.f
-sim_harness_blackboxes ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
-sim_top_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.top.f
+
+sim_files                  ?= $(build_dir)/sim_files.f
+sim_top_blackboxes         ?= $(build_dir)/firrtl_black_box_resource_files.top.f
+sim_harness_blackboxes     ?= $(build_dir)/firrtl_black_box_resource_files.harness.f
+sim_common_files           ?= $(build_dir)/sim_files.common.f

 #########################################################################################
 # java arguments used in sbt
@@ -167,9 +171,9 @@ rocketchip_vsrc_dir = $(ROCKETCHIP_DIR)/src/main/resources/vsrc
 # sources needed to run simulators
 #########################################################################################
 sim_vsrcs = \
-	$(VERILOG_FILE) \
+	$(TOP_FILE) \
 	$(HARNESS_FILE) \
-	$(SMEMS_FILE) \
+	$(TOP_SMEMS_FILE) \
 	$(HARNESS_SMEMS_FILE)

 #########################################################################################