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Update BridgeBinders with new HarnessRAM clocking

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This commit is contained in:
Jerry Zhao
2021-03-15 12:45:40 -07:00
parent c27c9d5d18
commit 8a78565c04
1 changed files with 3 additions and 2 deletions
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5
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -70,8 +70,9 @@ class WithSerialBridge extends OverrideHarnessBinder({
(system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => {
ports.map { port => ports.map { port =>
implicit val p = GetSystemParameters(system) implicit val p = GetSystemParameters(system)
val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset)
SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset)
SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName))
} }
Nil Nil
} }