From 8a78565c04d49ba6d4ccf569009ad0d17ca3fdaf Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 15 Mar 2021 12:45:40 -0700 Subject: [PATCH] Update BridgeBinders with new HarnessRAM clocking --- generators/firechip/src/main/scala/BridgeBinders.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index bdbb7d44..f0b376d0 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -70,8 +70,9 @@ class WithSerialBridge extends OverrideHarnessBinder({ (system: CanHavePeripheryTLSerial, th: FireSim, ports: Seq[ClockedIO[SerialIO]]) => { ports.map { port => implicit val p = GetSystemParameters(system) - val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, port, th.harnessReset) - SerialBridge(port.clock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) + val bits = SerialAdapter.asyncQueue(port, th.harnessClock, th.harnessReset) + val ram = SerialAdapter.connectHarnessRAM(system.serdesser.get, bits, th.harnessReset) + SerialBridge(th.harnessClock, ram.module.io.tsi_ser, p(ExtMem).map(_ => MainMemoryConsts.globalName)) } Nil }