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Support firrtl output in command line for MacroCompiler (#28)

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* Use the given port prefix (fix a bug preventing two unit tests from passing)
* Support firrtl output in addition to Verilog
This commit is contained in:
edwardcwang
2017-12-04 15:12:42 -08:00
committed by GitHub
parent c884a2fb15
commit 8a30579a3e
2 changed files with 33 additions and 11 deletions
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4
macros/src/test/scala/MacroCompilerSpec.scala
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@@ -335,7 +335,7 @@ s"""
* @param readEnable Has a read enable port?
* @param mask Mask granularity (# bits) of the port or None. */
def generateReadWriteFooterPort(prefix: String, readEnable: Boolean, mask: Option[Int]): String = {
generatePort(libPortPrefix, lib_addr_width, libWidth,
generatePort(prefix, lib_addr_width, libWidth,
write=true, writeEnable=true, read=true, readEnable=readEnable, mask)
}
@@ -344,7 +344,7 @@ s"""
* @param readEnable Has a read enable port?
* @param mask Mask granularity (# bits) of the port or None. */
def generateReadWriteHeaderPort(prefix: String, readEnable: Boolean, mask: Option[Int]): String = {
generatePort(memPortPrefix, mem_addr_width, memWidth,
generatePort(prefix, mem_addr_width, memWidth,
write=true, writeEnable=true, read=true, readEnable=readEnable, mask)
}