Merge remote-tracking branch 'origin/main' into tetheredsim

2023-05-31 21:55:09 -07:00
parent 592f1897e9 2aca0e23aa
commit 89db2372c3
52 changed files with 857 additions and 670 deletions
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -84,7 +84,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
    name = "chip_ddr",
    sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
  )))))
-  ddrNode := ddrClient
+  ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient

  // module implementation
  override lazy val module = new VCU118FPGATestHarnessImp(this)