diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 2d471e9e..85e4cc1b 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -33,7 +33,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spif
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
-grouping["group-other"]="icenet testchipip constellation"
+grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
 grouping["group-fpga"]="arty vcu118 vc707"
 
 # key value store to get the build strings
@@ -70,6 +70,10 @@ mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
 mapping["icenet"]="SUB_PROJECT=icenet"
 mapping["testchipip"]="SUB_PROJECT=testchipip"
+mapping["rocketchip-amba"]="SUB_PROJECT=rocketchip CONFIG=AMBAUnitTestConfig"
+mapping["rocketchip-tlsimple"]="SUB_PROJECT=rocketchip CONFIG=TLSimpleUnitTestConfig"
+mapping["rocketchip-tlwidth"]="SUB_PROJECT=rocketchip CONFIG=TLWidthUnitTestConfig"
+mapping["rocketchip-tlxbar"]="SUB_PROJECT=rocketchip CONFIG=TLXbarUnitTestConfig"
 
 mapping["arty"]="SUB_PROJECT=arty verilog"
 mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"
diff --git a/.github/scripts/run-tests.sh b/.github/scripts/run-tests.sh
index 2c3a6af7..89859eb7 100755
--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -139,6 +139,18 @@ case $1 in
     constellation)
         run_binary BINARY=none
         ;;
+    rocketchip-amba)
+        run_binary BINARY=none
+        ;;
+    rocketchip-tlsimple)
+        run_binary BINARY=none
+        ;;
+    rocketchip-tlwidth)
+        run_binary BINARY=none
+        ;;
+    rocketchip-tlxbar)
+        run_binary BINARY=none
+        ;;
     *)
         echo "No set of tests for $1. Did you spell it right?"
         exit 1
diff --git a/.github/workflows/chipyard-full-flow.yml b/.github/workflows/chipyard-full-flow.yml
index 5179be0f..50e219e3 100644
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -80,7 +80,7 @@ jobs:
           eval "$(conda shell.bash hook)"
           mkdir ${{ env.JAVA_TMP_DIR }}
           export MAKEFLAGS="-j32"
-          ./build-setup.sh -f
+          ./build-setup.sh -f -v
 
   run-cfg-finder:
     name: run-cfg-finder
@@ -115,7 +115,7 @@ jobs:
 
           cd vlsi
 
-          # NOTE: most conda installs are in separate conda envs because they mess up 
+          # NOTE: most conda installs are in separate conda envs because they mess up
           #   each other's versions (for no apparent reason) and we need the latest versions
           conda config --add channels defaults
           conda config --add channels litex-hub
@@ -166,7 +166,7 @@ jobs:
     name: cleanup
     needs: [run-tutorial]
     runs-on: ferry
-    if: ${{ always() && contains(join(needs.*.result, ','), 'success') }}
+    if: ${{ always() }}
     steps:
       - name: Delete repo copy and conda env
         run: |
diff --git a/.github/workflows/chipyard-run-tests.yml b/.github/workflows/chipyard-run-tests.yml
index f8ca8e11..72d6f654 100644
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -880,6 +880,45 @@ jobs:
           group-key: "group-other"
           project-key: "testchipip"
 
+  rocketchip-run-tests:
+    name: rocketchip-run-tests
+    needs: prepare-chipyard-other
+    runs-on: self-hosted
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run amba tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-other"
+          project-key: "rocketchip-amba"
+      # Below tests segfault with verilator, work fine in VCS
+      # - name: Run tlsimple tests
+      #   uses: ./.github/actions/run-tests
+      #   with:
+      #     group-key: "group-other"
+      #     project-key: "rocketchip-tlsimple"
+      # - name: Run tlwidth tests
+      #   uses: ./.github/actions/run-tests
+      #   with:
+      #     group-key: "group-other"
+      #     project-key: "rocketchip-tlwidth"
+      # - name: Run tlxbar tests
+      #   uses: ./.github/actions/run-tests
+      #   with:
+      #     group-key: "group-other"
+      #     project-key: "rocketchip-tlxbar"
+
   constellation-run-tests:
     name: constellation-run-tests
     needs: prepare-chipyard-other
@@ -1004,6 +1043,7 @@ jobs:
             tracegen-run-tests,
             icenet-run-tests,
             testchipip-run-tests,
+            rocketchip-run-tests,
             constellation-run-tests,
             prepare-chipyard-fpga, # firesim-run-tests,
             fireboom-run-tests]
diff --git a/.gitignore b/.gitignore
index 9c73c6e1..ac8e84d0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -26,3 +26,4 @@ project/metals.sbt
 project/project/
 .ivy2
 .sbt
+.classpath_cache/
diff --git a/build.sbt b/build.sbt
index 8160a4f9..6f72940a 100644
--- a/build.sbt
+++ b/build.sbt
@@ -4,14 +4,34 @@ import Tests._
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))
 
+// keep chisel/firrtl specific class files, rename other conflicts
+val chiselFirrtlMergeStrategy = CustomMergeStrategy.rename { dep =>
+  import sbtassembly.Assembly.{Project, Library}
+  val nm = dep match {
+    case p: Project => p.name
+    case l: Library => l.moduleCoord.name
+  }
+  if (Seq("firrtl", "chisel3").contains(nm.split("_")(0))) { // split by _ to avoid checking on major/minor version
+    dep.target
+  } else {
+    "renamed/" + dep.target
+  }
+}
+
 lazy val commonSettings = Seq(
   organization := "edu.berkeley.cs",
   version := "1.6",
   scalaVersion := "2.13.10",
   assembly / test := {},
-  assembly / assemblyMergeStrategy := { _ match {
-    case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
-    case _ => MergeStrategy.first}},
+  assembly / assemblyMergeStrategy := {
+    case PathList("chisel3", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    case PathList("firrtl", "stage", xs @ _*) => chiselFirrtlMergeStrategy
+    // should be safe in JDK11: https://stackoverflow.com/questions/54834125/sbt-assembly-deduplicate-module-info-class
+    case x if x.endsWith("module-info.class") => MergeStrategy.discard
+    case x =>
+      val oldStrategy = (assembly / assemblyMergeStrategy).value
+      oldStrategy(x)
+  },
   scalacOptions ++= Seq(
     "-deprecation",
     "-unchecked",
@@ -86,8 +106,6 @@ lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
   .settings(commonSettings)
   .settings(
     libraryDependencies ++= Seq(
-      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
       "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
@@ -97,8 +115,6 @@ lazy val rocketMacros  = (project in rocketChipDir / "macros")
   .settings(
     libraryDependencies ++= Seq(
       "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-      "org.json4s" %% "json4s-jackson" % "3.6.6",
-      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
     )
   )
 
@@ -225,7 +241,6 @@ lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "sr
 lazy val tapeout = (project in file("./tools/barstools/"))
   .settings(chiselSettings)
   .settings(chiselTestSettings)
-  .enablePlugins(sbtassembly.AssemblyPlugin)
   .settings(commonSettings)
 
 lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
diff --git a/common.mk b/common.mk
index 4501c20a..54f81cf6 100644
--- a/common.mk
+++ b/common.mk
@@ -16,7 +16,6 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_LDFLAGS         = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES         = additional simulation sources needed for simulator" \
 "   EXTRA_SIM_REQS            = additional make requirements to build the simulator" \
-"   ENABLE_SBT_THIN_CLIENT    = if set, use sbt's experimental thin client (works best when overridding SBT_BIN with the mainline sbt script)" \
 "   ENABLE_CUSTOM_FIRRTL_PASS = if set, enable custom firrtl passes (SFC lowers to LowFIRRTL & MFC converts to Verilog)" \
 "   ENABLE_YOSYS_FLOW         = if set, add compilation flags to enable the vlsi flow for yosys(tutorial flow)" \
 "   EXTRA_CHISEL_OPTIONS      = additional options to pass to the Chisel compiler" \
@@ -52,7 +51,6 @@ HELP_COMMANDS += \
 "   firrtl                      = generate intermediate firrtl files from chisel elaboration" \
 "   run-tests                   = run all assembly and benchmark tests" \
 "   launch-sbt                  = start sbt terminal" \
-"   {shutdown,start}-sbt-server = shutdown or start sbt server if using ENABLE_SBT_THIN_CLIENT" \
 "   find-config-fragments       = list all config. fragments"
 
 #########################################################################################
@@ -105,12 +103,24 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
 	cp -f $< $@
 
 #########################################################################################
-# create firrtl file rule and variables
+# compile scala jars
+#########################################################################################
+$(CHIPYARD_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS)
+	mkdir -p $(dir $@)
+	$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
+
+# order only dependency between sbt runs needed to avoid concurrent sbt runs
+$(TAPEOUT_CLASSPATH_TARGETS) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) | $(CHIPYARD_CLASSPATH_TARGETS)
+	mkdir -p $(dir $@)
+	$(call run_sbt_assembly,tapeout,$(TAPEOUT_CLASSPATH))
+
+#########################################################################################
+# verilog generation pipeline
 #########################################################################################
 # AG: must re-elaborate if cva6 sources have changed... otherwise just run firrtl compile
-$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(EXTRA_GENERATOR_REQS)
+$(FIRRTL_FILE) $(ANNO_FILE) $(CHISEL_LOG_FILE) &: $(CHIPYARD_CLASSPATH_TARGETS) $(EXTRA_GENERATOR_REQS)
 	mkdir -p $(build_dir)
-	(set -o pipefail && $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
+	(set -o pipefail && $(call run_jar_scala_main,$(CHIPYARD_CLASSPATH),$(GENERATOR_PACKAGE).Generator,\
 		--target-dir $(build_dir) \
 		--name $(long_name) \
 		--top-module $(MODEL_PACKAGE).$(MODEL) \
@@ -195,9 +205,9 @@ endif
 	if [ $(SFC_LEVEL) = none ]; then cat $(EXTRA_ANNO_FILE) > $(FINAL_ANNO_FILE); fi
 
 $(SFC_MFC_TARGETS) &: private TMP_DIR := $(shell mktemp -d -t cy-XXXXXXXX)
-$(SFC_MFC_TARGETS) &: $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
+$(SFC_MFC_TARGETS) &: $(TAPEOUT_CLASSPATH_TARGETS) $(FIRRTL_FILE) $(FINAL_ANNO_FILE) $(SFC_LEVEL) $(EXTRA_FIRRTL_OPTIONS)
 	rm -rf $(GEN_COLLATERAL_DIR)
-	$(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateModelStageMain,\
+	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.tapeout.transforms.GenerateModelStageMain,\
 		--no-dedup \
 		--output-file $(SFC_FIRRTL_BASENAME) \
 		--output-annotation-file $(SFC_ANNO_FILE) \
@@ -263,12 +273,12 @@ $(TOP_SMEMS_CONF) $(MODEL_SMEMS_CONF) &:  $(MFC_SMEMS_CONF) $(MFC_MODEL_HRCHY_JS
 
 # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
 TOP_MACROCOMPILER_MODE ?= --mode synflops
-$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TOP_SMEMS_CONF)
-	$(call run_scala_main,tapeout,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
+$(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(TOP_SMEMS_CONF)
+	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(TOP_MACROCOMPILER_MODE))
 
 MODEL_MACROCOMPILER_MODE = --mode synflops
-$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
-	$(call run_scala_main,tapeout,barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
+$(MODEL_SMEMS_FILE) $(MODEL_SMEMS_FIR) &: $(TAPEOUT_CLASSPATH_TARGETS) $(MODEL_SMEMS_CONF) | $(TOP_SMEMS_FILE)
+	$(call run_jar_scala_main,$(TAPEOUT_CLASSPATH),barstools.macros.MacroCompiler, -n $(MODEL_SMEMS_CONF) -v $(MODEL_SMEMS_FILE) -f $(MODEL_SMEMS_FIR) $(MODEL_MACROCOMPILER_MODE))
 
 ########################################################################################
 # remove duplicate files and headers in list of simulation file inputs
@@ -391,7 +401,6 @@ endif
 #######################################
 # Rules for building DRAMSim2 library
 #######################################
-
 dramsim_dir = $(base_dir)/tools/DRAMSim2
 dramsim_lib = $(dramsim_dir)/libdramsim.a
 
@@ -399,27 +408,12 @@ $(dramsim_lib):
 	$(MAKE) -C $(dramsim_dir) $(notdir $@)
 
 ################################################
-# Helper to run SBT or manage the SBT server
+# Helper to run SBT
 ################################################
-
 SBT_COMMAND ?= shell
 .PHONY: launch-sbt
 launch-sbt:
-	cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)"
-
-.PHONY: check-thin-client
-check-thin-client:
-ifeq (,$(ENABLE_SBT_THIN_CLIENT))
-	$(error ENABLE_SBT_THIN_CLIENT not set.)
-endif
-
-.PHONY: shutdown-sbt-server
-shutdown-sbt-server: check-thin-client
-	cd $(base_dir) && $(SBT) "shutdown"
-
-.PHONY: start-sbt-server
-start-sbt-server: check-thin-client
-	cd $(base_dir) && $(SBT) "exit"
+	cd $(base_dir) && $(SBT) "$(SBT_COMMAND)"
 
 #########################################################################################
 # print help text (and other help)
diff --git a/conda-reqs/chipyard.yaml b/conda-reqs/chipyard.yaml
index d1d9eab9..d67f3452 100644
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -93,7 +93,7 @@ dependencies:
     - screen
     - elfutils
     - libdwarf-dev==0.0.0.20190110_28_ga81397fc4 # from ucb-bar channel - using mainline libdwarf-feedstock
-    - conda-lock>=1
+    - conda-lock=1
 
     # clang-format for driver coding style enforcement.
     - clang-format
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
index 4899b455..d35ed064 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
@@ -7,9 +7,9 @@
 # Install this environment as "YOURENV" with:
 #     conda-lock install -n YOURENV --file conda-requirements-esp-tools-linux-64.conda-lock.yml
 # To update a single package to the latest version compatible with the version constraints in the source:
-#     conda-lock lock  --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE
+#     conda-lock lock --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
+#     conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml -f /scratch/abejgonza/cy-check/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-check/conda-reqs/esp-tools.yaml --lockfile conda-requirements-esp-tools-linux-64.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,12 +21,14 @@ metadata:
   - url: nodefaults
     used_env_vars: []
   content_hash:
-    linux-64: 86382a6fa6e58883c85e482f6c209ab347df1461d7c5706f28b95813412dfe94
+    linux-64: 9600a29dfc36e0d5f74716881b8020b4deb08672489e89923b0036ca29e44589
   platforms:
   - linux-64
   sources:
   - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml
   - /scratch/abejgonza/cy/conda-reqs/esp-tools.yaml
+  - /scratch/abejgonza/cy-check/conda-reqs/chipyard.yaml
+  - /scratch/abejgonza/cy-check/conda-reqs/esp-tools.yaml
 package:
 - category: main
   dependencies: {}
@@ -234,14 +236,14 @@ package:
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
   hash:
-    md5: 523bc836a954faf0cca94831971bb85a
-    sha256: 67a3caa56e2a59f407f3d290437b865aaf996873006e2fcfca6295d0f0be8db9
+    md5: 540e9f635ce30eb7fbf4488cfcf656bf
+    sha256: b0a77e609081d5a03327fd718c713fe83671043fdcd97f5983a1e956fe4d3052
   manager: conda
   name: kernel-headers_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
-  version: 3.10.0
+  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-4.18.0-he073ed8_0.conda
+  version: 4.18.0
 - category: main
   dependencies:
     libgfortran5: 12.2.0 h337968e_19
@@ -294,16 +296,16 @@ package:
 - category: main
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
-    kernel-headers_linux-64: 3.10.0 h4a8ded7_13
+    kernel-headers_linux-64: 4.18.0 he073ed8_0
   hash:
-    md5: 57e5a5191ffe999b9f4dfdbcd0ddcba4
-    sha256: f09f2fea4b571dcd225f1e35bd3c851e809cd4c2f5f151438133969ab28478e5
+    md5: f55932f8af2630b906d746c374028226
+    sha256: cbcaffe5c8df0e0e3e3110582b666b154482a1517233836b3ec2b2aa122dd7fb
   manager: conda
   name: sysroot_linux-64
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_13.tar.bz2
-  version: '2.17'
+  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.28-he073ed8_0.conda
+  version: '2.28'
 - category: main
   dependencies:
     ld_impl_linux-64: 2.40 h41732ed_0
@@ -334,14 +336,14 @@ package:
   dependencies:
     libgcc-ng: '>=12'
   hash:
-    md5: be733e69048951df1e4b4b7bb8c7666f
-    sha256: 2c0a618d0fa695e4e01a30e7ff31094be540c52e9085cbd724edb132c65cf9cd
+    md5: a0c6f0e7e1a467f5678f94dea18c8aa7
+    sha256: f177627acdfcead15a28f4a07fcda6a1e26b83f053eaa1efa7cce01c0a3b09a8
   manager: conda
   name: alsa-lib
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.8-h166bdaf_0.tar.bz2
-  version: 1.2.8
+  url: https://conda.anaconda.org/conda-forge/linux-64/alsa-lib-1.2.9-hd590300_0.conda
+  version: 1.2.9
 - category: main
   dependencies:
     libgcc-ng: '>=9.4.0'
@@ -380,16 +382,16 @@ package:
   version: 1.0.8
 - category: main
   dependencies:
-    libgcc-ng: '>=9.4.0'
+    libgcc-ng: '>=12'
   hash:
-    md5: f26ef8098fab1f719c91eb760d63381a
-    sha256: ee735e60d2cf68e5635df17847e97b505a752985d10581d2438203e7c0f44c15
+    md5: e8c18d865be43e2fb3f7a145b6adf1f5
+    sha256: c4276b1a0e8f18ab08018b1881666656742b325e0fcf2354f714e924d28683b6
   manager: conda
   name: c-ares
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.18.1-h7f98852_0.tar.bz2
-  version: 1.18.1
+  url: https://conda.anaconda.org/conda-forge/linux-64/c-ares-1.19.1-hd590300_0.conda
+  version: 1.19.1
 - category: main
   dependencies:
     libgcc-ng: '>=12'
@@ -420,6 +422,7 @@ package:
     libstdcxx-ng: '>=12'
   hash:
     md5: 6bfb79319763a11c7423c9d0e0ee00b7
+    sha256: null
   manager: conda
   name: dromajo
   optional: false
@@ -551,6 +554,19 @@ package:
   platform: linux-64
   url: https://conda.anaconda.org/conda-forge/linux-64/lerc-4.0.0-h27087fc_0.tar.bz2
   version: 4.0.0
+- category: main
+  dependencies:
+    libgcc-ng: '>=12'
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     fribidi: '>=1.0.10,<2.0a0'
-    harfbuzz: '>=6.0.0,<7.0a0'
+    harfbuzz: '>=7.1.0,<8.0a0'
     libgcc-ng: '>=12'
-    libglib: '>=2.74.1,<3.0a0'
+    libglib: '>=2.76.1,<3.0a0'
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-  url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-hd33c08f_0.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-heaa33ce_1.conda
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 - category: main
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@@ -4599,27 +4619,28 @@ package:
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-  url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.1.0-pyhd8ed1ab_0.conda
-  version: 3.1.0
+  url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.2.0-pyhd8ed1ab_0.conda
+  version: 3.2.0
 - category: main
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   optional: false
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-  url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.1.1-pyhd8ed1ab_0.conda
-  version: 23.1.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-21.0.0-pyhd8ed1ab_0.tar.bz2
+  version: 21.0.0
 - category: main
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@@ -4827,14 +4848,14 @@ package:
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-  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.1-pyha770c72_0.conda
-  version: 3.3.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.2-pyha770c72_0.conda
+  version: 3.3.2
 - category: main
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@@ -4873,14 +4894,14 @@ package:
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   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.131-pyhd8ed1ab_0.conda
-  version: 1.29.131
+  url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.142-pyhd8ed1ab_0.conda
+  version: 1.29.142
 - category: main
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@@ -4917,16 +4938,16 @@ package:
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     idna: '>=2.5,<4'
     python: '>=3.7'
-    urllib3: '>=1.21.1,<1.27'
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-    sha256: bd06a6603104050fc9c4fd9bf3de7b28bbb6b9ce4b33130519d8611488213f67
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   manager: conda
   name: requests
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/requests-2.29.0-pyhd8ed1ab_0.conda
-  version: 2.29.0
+  url: https://conda.anaconda.org/conda-forge/noarch/requests-2.31.0-pyhd8ed1ab_0.conda
+  version: 2.31.0
 - category: main
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@@ -5112,7 +5133,7 @@ package:
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 - category: main
   dependencies:
-    botocore: 1.29.131
+    botocore: 1.29.142
     colorama: '>=0.2.5,<0.4.5'
     docutils: '>=0.10,<0.17'
     python: '>=3.9,<3.10.0a0'
@@ -5121,29 +5142,29 @@ package:
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     s3transfer: '>=0.6.0,<0.7.0'
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-    sha256: e26260e3439d5a1b350fe9b244230c0ed2356a4ee873ddbb59a1f2cfa839b627
+    md5: 9dab1670819ad5d8e393e75f349bf523
+    sha256: 49f4b45526276cf994af5186cec4eb02dd84a58bfa9c35451c30b6a7cbe22a69
   manager: conda
   name: awscli
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.131-py39hf3d152e_0.conda
-  version: 1.27.131
+  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.142-py39hf3d152e_0.conda
+  version: 1.27.142
 - category: main
   dependencies:
-    botocore: '>=1.29.131,<1.30.0'
+    botocore: '>=1.29.142,<1.30.0'
     jmespath: '>=0.7.1,<2.0.0'
     python: '>=3.7'
     s3transfer: '>=0.6.0,<0.7.0'
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-    sha256: 888fa362ba6db8b881a200539c1cc4379379ec1937168e5e475245fa1a3544c7
+    md5: 7183f27eb377ee481de34fbcfa40b67e
+    sha256: fd2fb41bcec9bd6b70d367d4d83c4fed054ee4c6853c422b67e55ea5cf233c86
   manager: conda
   name: boto3
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.131-pyhd8ed1ab_0.conda
-  version: 1.26.131
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.142-pyhd8ed1ab_0.conda
+  version: 1.26.142
 - category: main
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@@ -5269,14 +5290,14 @@ package:
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     typing_extensions: ''
   hash:
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-    sha256: d18385d39e4af117b99cbd931cb68cbd33582949a837ae4e6453964ecc64d80a
+    md5: e4035713762b745fe7521141eef9cbec
+    sha256: d0f14dcdaf50e693a5a3422945cf034587b9c19e0b41ef04a8525b3f5418e737
   manager: conda
   name: boto3-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.130-pyhd8ed1ab_0.conda
-  version: 1.26.130
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.143-pyhd8ed1ab_0.conda
+  version: 1.26.143
 - category: main
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@@ -5331,14 +5352,14 @@ package:
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     typing-extensions: ''
   hash:
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-    sha256: 706be4a8f070af47d29e18315c3053977315c1c58479ecfebb2443d3a72edf87
+    md5: 2f58c5525f108a1525553e081c90f815
+    sha256: 66d980a4aa02be974410c64d0631ea54d26e538f49300ac5e3b46d44a4acec78
   manager: conda
   name: mypy_boto3_ec2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.129-pyhd8ed1ab_0.conda
-  version: 1.26.129
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.136-pyhd8ed1ab_0.conda
+  version: 1.26.136
 - category: main
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@@ -5360,14 +5381,14 @@ package:
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     sphinxcontrib-jquery: '>=2.0.0,!=3.0.0'
   hash:
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-    sha256: 3774803e81091a64d2f3990246bb9310f1b9df13887914e1c77eab917bf102ec
+    md5: dd1ec3c6beac662d7bf9c996975f637f
+    sha256: 818659eb58b74da694e7ff6ecb907d417ae0de4db8231c42f0b0ba75f56ef3f4
   manager: conda
   name: sphinx_rtd_theme
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.2.0-pyha770c72_0.conda
-  version: 1.2.0
+  url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.2.1-pyha770c72_0.conda
+  version: 1.2.1
 - category: main
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     aws-sam-translator: '>=1.55.0'
@@ -5417,14 +5438,14 @@ package:
     werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
     xmltodict: ''
   hash:
-    md5: 89dfb6776dcc992a100cafd0c612b7fb
-    sha256: f5de61e07e99798c0f73947fae9f947a4eb7aeff7adc04e78b9a9a3ef2ddc780
+    md5: 7f8865d0f6df238a407cab06d884c211
+    sha256: c51cc65dac1b0b1f5139860c07030b9465417cebcb8529ffa97fcd8615aba606
   manager: conda
   name: moto
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.9-pyhd8ed1ab_0.conda
-  version: 4.1.9
+  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.10-pyhd8ed1ab_0.conda
+  version: 4.1.10
 - category: main
   dependencies: {}
   hash:
@@ -5433,6 +5454,7 @@ package:
   name: mock
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/27/6f/fbb16f260a7107ee98871d83f6793d88c4311b7189b10ef239da0b2181db/mock-5.0.2-py3-none-any.whl
   version: 5.0.2
 - dependencies: {}
@@ -5441,6 +5463,7 @@ package:
   manager: pip
   name: pyyaml
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/12/fc/a4d5a7554e0067677823f7265cb3ae22aed8a238560b5133b58cda252dad/PyYAML-6.0-cp39-cp39-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl
   version: '6.0'
 - category: main
@@ -5452,6 +5475,7 @@ package:
   name: asttokens
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl
   version: 2.2.1
 - category: main
@@ -5463,6 +5487,7 @@ package:
   name: gdspy
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/1d/e4/97b8add92fbec2a9890ad4777272e9a9e4d7a0ceeac42b7e1febe94f0e86/gdspy-1.4.zip
   version: '1.4'
 - category: main
@@ -5475,6 +5500,7 @@ package:
   name: paramiko-ng
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl
   version: 2.8.10
 - category: main
@@ -5486,6 +5512,7 @@ package:
   name: ruamel.yaml
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/23/33/dbc62343de0cf92e0f9c15bc0a287bdaea0953f1cadca0480c78d5ac6641/ruamel.yaml-0.17.26-py3-none-any.whl
   version: 0.17.26
 - category: main
@@ -5498,6 +5525,7 @@ package:
   name: sure
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/dd/ae/eb28ee3b6768e51cb938abcf521cb678217203f33385a2df54d3f23331c5/sure-2.0.1.tar.gz
   version: 2.0.1
 - category: main
@@ -5510,6 +5538,7 @@ package:
   name: fab-classic
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/6b/0f/efc537eebfd2a2c470250c0ac8bd8a05ffc13d95a7fb22021367890d7c46/fab_classic-1.19.2-py2.py3-none-any.whl
   version: 1.19.2
 - category: main
@@ -5525,6 +5554,7 @@ package:
   name: hammer-vlsi
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/0a/da/1897421311c6332655e2f73d02d8c914ecb724198a1988aacd8f4c61ae6e/hammer_vlsi-1.1.1-py3-none-any.whl
   version: 1.1.1
 - category: main
@@ -5537,6 +5567,7 @@ package:
   name: icontract
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/d8/91/9756e7cf0b155e80bf9a62beffdd1dec4afce43cc6ab7f432f2267c62762/icontract-2.6.2-py3-none-any.whl
   version: 2.6.2
 - category: main
@@ -5549,6 +5580,7 @@ package:
   name: pylddwrap
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz
   version: 1.2.2
 version: 1
diff --git a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
index 22681575..6ccfa40f 100644
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
@@ -7,9 +7,9 @@
 # Install this environment as "YOURENV" with:
 #     conda-lock install -n YOURENV --file conda-requirements-riscv-tools-linux-64.conda-lock.yml
 # To update a single package to the latest version compatible with the version constraints in the source:
-#     conda-lock lock  --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE
+#     conda-lock lock --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml --update PACKAGE
 # To re-solve the entire environment, e.g. after changing a version constraint in the source file:
-#     conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
+#     conda-lock -f /scratch/abejgonza/cy/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml -f /scratch/abejgonza/cy-check/conda-reqs/chipyard.yaml -f /scratch/abejgonza/cy-check/conda-reqs/riscv-tools.yaml --lockfile conda-requirements-riscv-tools-linux-64.conda-lock.yml
 metadata:
   channels:
   - url: ucb-bar
@@ -21,12 +21,14 @@ metadata:
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     used_env_vars: []
   content_hash:
-    linux-64: 92c3e7798f0b770b5c7c3ccb9bb821f7aca74819a9dba397e47d752af976b25f
+    linux-64: b0ec35c8fb9744ff1f54090428e86cb2c026ee4fb1441cf49d7492c212878158
   platforms:
   - linux-64
   sources:
   - /scratch/abejgonza/cy/conda-reqs/chipyard.yaml
   - /scratch/abejgonza/cy/conda-reqs/riscv-tools.yaml
+  - /scratch/abejgonza/cy-check/conda-reqs/chipyard.yaml
+  - /scratch/abejgonza/cy-check/conda-reqs/riscv-tools.yaml
 package:
 - category: main
   dependencies: {}
@@ -234,14 +236,14 @@ package:
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     _sysroot_linux-64_curr_repodata_hack: 3.*
   hash:
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-    sha256: 67a3caa56e2a59f407f3d290437b865aaf996873006e2fcfca6295d0f0be8db9
+    md5: 540e9f635ce30eb7fbf4488cfcf656bf
+    sha256: b0a77e609081d5a03327fd718c713fe83671043fdcd97f5983a1e956fe4d3052
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   name: kernel-headers_linux-64
   optional: false
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-  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-3.10.0-h4a8ded7_13.tar.bz2
-  version: 3.10.0
+  url: https://conda.anaconda.org/conda-forge/noarch/kernel-headers_linux-64-4.18.0-he073ed8_0.conda
+  version: 4.18.0
 - category: main
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@@ -294,16 +296,16 @@ package:
 - category: main
   dependencies:
     _sysroot_linux-64_curr_repodata_hack: 3.*
-    kernel-headers_linux-64: 3.10.0 h4a8ded7_13
+    kernel-headers_linux-64: 4.18.0 he073ed8_0
   hash:
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-    sha256: f09f2fea4b571dcd225f1e35bd3c851e809cd4c2f5f151438133969ab28478e5
+    md5: f55932f8af2630b906d746c374028226
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   manager: conda
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   optional: false
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-  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.17-h4a8ded7_13.tar.bz2
-  version: '2.17'
+  url: https://conda.anaconda.org/conda-forge/noarch/sysroot_linux-64-2.28-he073ed8_0.conda
+  version: '2.28'
 - category: main
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@@ -334,14 +336,14 @@ package:
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     libgcc-ng: '>=12'
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+    md5: a0c6f0e7e1a467f5678f94dea18c8aa7
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   name: clang-tools
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.3-default_h83cc7fd_0.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/clang-tools-16.0.3-default_h1cdf331_2.conda
   version: 16.0.3
 - category: main
   dependencies:
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-  version: 0.7.0
+  url: https://conda.anaconda.org/conda-forge/noarch/conda-package-streaming-0.8.0-pyhd8ed1ab_0.conda
+  version: 0.8.0
 - category: main
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@@ -4499,6 +4517,7 @@ package:
     libzlib: '>=1.2.12,<1.3.0a0'
   hash:
     md5: 899c511688e6c41cb51c2921a8d25e63
+    sha256: null
   manager: conda
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@@ -4520,12 +4539,12 @@ package:
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 - category: main
   dependencies:
-    alsa-lib: '>=1.2.8,<1.2.9.0a0'
+    alsa-lib: '>=1.2.9,<1.2.10.0a0'
     fontconfig: '>=2.14.2,<3.0a0'
     fonts-conda-ecosystem: ''
     freetype: '>=2.12.1,<3.0a0'
     giflib: '>=5.2.1,<5.3.0a0'
-    harfbuzz: '>=6.0.0,<7.0a0'
+    harfbuzz: '>=7.3.0,<8.0a0'
     lcms2: '>=2.15,<3.0a0'
     libcups: '>=2.3.3,<2.4.0a0'
     libgcc-ng: '>=12'
@@ -4539,13 +4558,13 @@ package:
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     xorg-libxtst: ''
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-    md5: 33527b036cd6d369be12fd772cdd49e4
-    sha256: 221de13214f051654177dd331c019a889ab1bbe3b2cf30d5cf17596378740359
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.3-h4335b31_6.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/openjdk-17.0.3-h8e330f5_8.conda
   version: 17.0.3
 - category: main
   dependencies:
@@ -4554,18 +4573,18 @@ package:
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     freetype: '>=2.12.1,<3.0a0'
     fribidi: '>=1.0.10,<2.0a0'
-    harfbuzz: '>=6.0.0,<7.0a0'
+    harfbuzz: '>=7.1.0,<8.0a0'
     libgcc-ng: '>=12'
-    libglib: '>=2.74.1,<3.0a0'
+    libglib: '>=2.76.1,<3.0a0'
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-hd33c08f_0.conda
+  url: https://conda.anaconda.org/conda-forge/linux-64/pango-1.50.14-heaa33ce_1.conda
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 - category: main
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@@ -4574,27 +4593,28 @@ package:
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   optional: false
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-  url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.1.0-pyhd8ed1ab_0.conda
-  version: 3.1.0
+  url: https://conda.anaconda.org/conda-forge/noarch/paramiko-3.2.0-pyhd8ed1ab_0.conda
+  version: 3.2.0
 - category: main
   dependencies:
-    cryptography: '>=38.0.0,<41'
-    python: '>=3.6'
+    cryptography: '>=3.3'
+    python: '>=2.7'
+    six: '>=1.5.2'
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-  url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-23.1.1-pyhd8ed1ab_0.conda
-  version: 23.1.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pyopenssl-21.0.0-pyhd8ed1ab_0.tar.bz2
+  version: 21.0.0
 - category: main
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@@ -4802,14 +4822,14 @@ package:
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-  version: 3.3.1
+  url: https://conda.anaconda.org/conda-forge/noarch/pre-commit-3.3.2-pyha770c72_0.conda
+  version: 3.3.2
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@@ -4848,14 +4868,14 @@ package:
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-  url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.131-pyhd8ed1ab_0.conda
-  version: 1.29.131
+  url: https://conda.anaconda.org/conda-forge/noarch/botocore-1.29.142-pyhd8ed1ab_0.conda
+  version: 1.29.142
 - category: main
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@@ -4892,16 +4912,16 @@ package:
     charset-normalizer: '>=2,<4'
     idna: '>=2.5,<4'
     python: '>=3.7'
-    urllib3: '>=1.21.1,<1.27'
+    urllib3: '>=1.21.1,<3'
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   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/requests-2.29.0-pyhd8ed1ab_0.conda
-  version: 2.29.0
+  url: https://conda.anaconda.org/conda-forge/noarch/requests-2.31.0-pyhd8ed1ab_0.conda
+  version: 2.31.0
 - category: main
   dependencies:
     botocore: '>=1.11.3'
@@ -5087,7 +5107,7 @@ package:
   version: 5.1.1
 - category: main
   dependencies:
-    botocore: 1.29.131
+    botocore: 1.29.142
     colorama: '>=0.2.5,<0.4.5'
     docutils: '>=0.10,<0.17'
     python: '>=3.10,<3.11.0a0'
@@ -5096,29 +5116,29 @@ package:
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+    md5: a12caee33189a2730faf21477e971491
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   manager: conda
   name: awscli
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.131-py310hff52083_0.conda
-  version: 1.27.131
+  url: https://conda.anaconda.org/conda-forge/linux-64/awscli-1.27.142-py310hff52083_0.conda
+  version: 1.27.142
 - category: main
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+    botocore: '>=1.29.142,<1.30.0'
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     s3transfer: '>=0.6.0,<0.7.0'
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   name: boto3
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.131-pyhd8ed1ab_0.conda
-  version: 1.26.131
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-1.26.142-pyhd8ed1ab_0.conda
+  version: 1.26.142
 - category: main
   dependencies:
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@@ -5244,14 +5264,14 @@ package:
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     typing_extensions: ''
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-    sha256: d18385d39e4af117b99cbd931cb68cbd33582949a837ae4e6453964ecc64d80a
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   manager: conda
   name: boto3-stubs
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.130-pyhd8ed1ab_0.conda
-  version: 1.26.130
+  url: https://conda.anaconda.org/conda-forge/noarch/boto3-stubs-1.26.143-pyhd8ed1ab_0.conda
+  version: 1.26.143
 - category: main
   dependencies:
     cachecontrol-with-filecache: '>=0.12.9'
@@ -5306,14 +5326,14 @@ package:
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     typing-extensions: ''
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-    sha256: 706be4a8f070af47d29e18315c3053977315c1c58479ecfebb2443d3a72edf87
+    md5: 2f58c5525f108a1525553e081c90f815
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   manager: conda
   name: mypy_boto3_ec2
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.129-pyhd8ed1ab_0.conda
-  version: 1.26.129
+  url: https://conda.anaconda.org/conda-forge/noarch/mypy_boto3_ec2-1.26.136-pyhd8ed1ab_0.conda
+  version: 1.26.136
 - category: main
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@@ -5335,14 +5355,14 @@ package:
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     sphinxcontrib-jquery: '>=2.0.0,!=3.0.0'
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-    sha256: 3774803e81091a64d2f3990246bb9310f1b9df13887914e1c77eab917bf102ec
+    md5: dd1ec3c6beac662d7bf9c996975f637f
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   manager: conda
   name: sphinx_rtd_theme
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.2.0-pyha770c72_0.conda
-  version: 1.2.0
+  url: https://conda.anaconda.org/conda-forge/noarch/sphinx_rtd_theme-1.2.1-pyha770c72_0.conda
+  version: 1.2.1
 - category: main
   dependencies:
     aws-sam-translator: '>=1.55.0'
@@ -5392,14 +5412,14 @@ package:
     werkzeug: '>=0.5,!=2.2.0,!=2.2.1'
     xmltodict: ''
   hash:
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-    sha256: f5de61e07e99798c0f73947fae9f947a4eb7aeff7adc04e78b9a9a3ef2ddc780
+    md5: 7f8865d0f6df238a407cab06d884c211
+    sha256: c51cc65dac1b0b1f5139860c07030b9465417cebcb8529ffa97fcd8615aba606
   manager: conda
   name: moto
   optional: false
   platform: linux-64
-  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.9-pyhd8ed1ab_0.conda
-  version: 4.1.9
+  url: https://conda.anaconda.org/conda-forge/noarch/moto-4.1.10-pyhd8ed1ab_0.conda
+  version: 4.1.10
 - category: main
   dependencies: {}
   hash:
@@ -5408,6 +5428,7 @@ package:
   name: mock
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/27/6f/fbb16f260a7107ee98871d83f6793d88c4311b7189b10ef239da0b2181db/mock-5.0.2-py3-none-any.whl
   version: 5.0.2
 - dependencies: {}
@@ -5416,6 +5437,7 @@ package:
   manager: pip
   name: pyyaml
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/02/25/6ba9f6bb50a3d4fbe22c1a02554dc670682a07c8701d1716d19ddea2c940/PyYAML-6.0-cp310-cp310-manylinux_2_5_x86_64.manylinux1_x86_64.manylinux_2_12_x86_64.manylinux2010_x86_64.whl
   version: '6.0'
 - category: main
@@ -5427,6 +5449,7 @@ package:
   name: asttokens
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/f3/e1/64679d9d0759db5b182222c81ff322c2fe2c31e156a59afd6e9208c960e5/asttokens-2.2.1-py2.py3-none-any.whl
   version: 2.2.1
 - category: main
@@ -5438,6 +5461,7 @@ package:
   name: gdspy
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/1d/e4/97b8add92fbec2a9890ad4777272e9a9e4d7a0ceeac42b7e1febe94f0e86/gdspy-1.4.zip
   version: '1.4'
 - category: main
@@ -5450,6 +5474,7 @@ package:
   name: paramiko-ng
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/9f/53/1ac75eab589149b1e02e38185ecebf09e1b805fc3fdeadbc16d1a2b7d208/paramiko_ng-2.8.10-py2.py3-none-any.whl
   version: 2.8.10
 - category: main
@@ -5461,6 +5486,7 @@ package:
   name: ruamel.yaml
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/23/33/dbc62343de0cf92e0f9c15bc0a287bdaea0953f1cadca0480c78d5ac6641/ruamel.yaml-0.17.26-py3-none-any.whl
   version: 0.17.26
 - category: main
@@ -5473,6 +5499,7 @@ package:
   name: sure
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/dd/ae/eb28ee3b6768e51cb938abcf521cb678217203f33385a2df54d3f23331c5/sure-2.0.1.tar.gz
   version: 2.0.1
 - category: main
@@ -5485,6 +5512,7 @@ package:
   name: fab-classic
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/6b/0f/efc537eebfd2a2c470250c0ac8bd8a05ffc13d95a7fb22021367890d7c46/fab_classic-1.19.2-py2.py3-none-any.whl
   version: 1.19.2
 - category: main
@@ -5500,6 +5528,7 @@ package:
   name: hammer-vlsi
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/0a/da/1897421311c6332655e2f73d02d8c914ecb724198a1988aacd8f4c61ae6e/hammer_vlsi-1.1.1-py3-none-any.whl
   version: 1.1.1
 - category: main
@@ -5512,6 +5541,7 @@ package:
   name: icontract
   optional: false
   platform: linux-64
+  source: null
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   version: 2.6.2
 - category: main
@@ -5524,6 +5554,7 @@ package:
   name: pylddwrap
   optional: false
   platform: linux-64
+  source: null
   url: https://files.pythonhosted.org/packages/c9/12/4afd6542c43cd20271f0e53bf0211decc10079a76a41e53c0288025a7b85/pylddwrap-1.2.2.tar.gz
   version: 1.2.2
 version: 1
diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
index 45263a14..87deef33 100644
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -46,7 +46,7 @@ This is done by the following:
 
 .. code-block:: shell
 
-    conda install -n base conda-lock
+    conda install -n base conda-lock=1
     conda activate base
 
 .. Note:: We also recommended switching to `libmamba <https://www.anaconda.com/blog/a-faster-conda-for-a-growing-community>`__ for much faster dependency solving.
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index 9f4c6ac5..d650f81c 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit 9f4c6ac5719b03ded61022dc3767e750872d0535
+Subproject commit d650f81c0728f3108719d37396c2a651a7463520
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index ac9f9d05..850b7f62 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -84,7 +84,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
     name = "chip_ddr",
     sourceId = IdRange(0, 1 << dp(ExtTLMem).get.master.idBits)
   )))))
-  ddrNode := ddrClient
+  ddrNode := TLWidthWidget(dp(ExtTLMem).get.master.beatBytes) := ddrClient
 
   // module implementation
   override lazy val module = new VCU118FPGATestHarnessImp(this)
diff --git a/generators/boom b/generators/boom
index 679f3587..f732ceb6 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 679f358755c57524f18cf46b72fc3fc1ac67f127
+Subproject commit f732ceb602bcccd4adb6a5f7137c7c0bea08be9d
diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala
index cee23413..de04b032 100644
--- a/generators/chipyard/src/main/scala/Cospike.scala
+++ b/generators/chipyard/src/main/scala/Cospike.scala
@@ -72,17 +72,18 @@ object SpikeCosim
     })
     cosim.io.hartid := hartid.U
     for (i <- 0 until trace.numInsns) {
-      cosim.io.trace(i).valid := trace.insns(i).valid
+      val insn = trace.trace.insns(i)
+      cosim.io.trace(i).valid := insn.valid
       val signed = Wire(SInt(64.W))
-      signed := trace.insns(i).iaddr.asSInt
+      signed := insn.iaddr.asSInt
       cosim.io.trace(i).iaddr := signed.asUInt
-      cosim.io.trace(i).insn := trace.insns(i).insn
-      cosim.io.trace(i).exception := trace.insns(i).exception
-      cosim.io.trace(i).interrupt := trace.insns(i).interrupt
-      cosim.io.trace(i).cause := trace.insns(i).cause
-      cosim.io.trace(i).has_wdata := trace.insns(i).wdata.isDefined.B
-      cosim.io.trace(i).wdata := trace.insns(i).wdata.getOrElse(0.U)
-      cosim.io.trace(i).priv := trace.insns(i).priv
+      cosim.io.trace(i).insn := insn.insn
+      cosim.io.trace(i).exception := insn.exception
+      cosim.io.trace(i).interrupt := insn.interrupt
+      cosim.io.trace(i).cause := insn.cause
+      cosim.io.trace(i).has_wdata := insn.wdata.isDefined.B
+      cosim.io.trace(i).wdata := insn.wdata.getOrElse(0.U)
+      cosim.io.trace(i).priv := insn.priv
     }
   }
 }
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index c6ec13ae..fc822c22 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -62,6 +62,7 @@ case class SpikeCoreParams() extends CoreParams {
   val useBitManipCrypto = false
   val useCryptoNIST = false
   val useCryptoSM = false
+  val useConditionalZero = false
 
   override def vLen = 128
   override def vMemDataBits = 128
diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
index 5618f582..9fa6f32b 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
     val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
     val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-    tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
-    tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
-    tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
+    clockDivider.tlNode  := system.prci_ctrl_bus
+    clockSelector.tlNode := system.prci_ctrl_bus
+    pllCtrl.tlNode       := system.prci_ctrl_bus
 
     system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
index ff6c52e9..e5236804 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -23,9 +23,9 @@ object ClockGroupCombiner {
 case object ClockGroupCombinerKey extends Field[Seq[(String, ClockSinkParameters => Boolean)]](Nil)
 
 // All clock groups with a name containing any substring in names will be combined into a single clock group
-class WithClockGroupsCombinedByName(groups: (String, Seq[String])*) extends Config((site, here, up) => {
-  case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names) =>
-    (grouped_name, (m: ClockSinkParameters) => matched_names.map(n => m.name.get.contains(n)).reduce(_||_))
+class WithClockGroupsCombinedByName(groups: (String, Seq[String], Seq[String])*) extends Config((site, here, up) => {
+  case ClockGroupCombinerKey => groups.map { case (grouped_name, matched_names, unmatched_names) =>
+    (grouped_name, (m: ClockSinkParameters) => matched_names.exists(n => m.name.get.contains(n)) && !unmatched_names.exists(n => m.name.get.contains(n)))
   }
 })
 
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
index 6a2c82ca..71010c66 100644
--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -36,6 +36,14 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
   val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
   prci_ctrl_domain.clockNode := tlbus.fixedClockNode
 
+  val prci_ctrl_bus = prci_ctrl_domain { TLXbar() }
+  tlbus.coupleTo("prci_ctrl") { (prci_ctrl_bus
+    := TLFIFOFixer(TLFIFOFixer.all)
+    := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes)
+    := TLBuffer()
+    := _)
+  }
+
   // Aggregate all the clock groups into a single node
   val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
   val allClockGroupsNode = ClockGroupEphemeralNode()
@@ -71,19 +79,24 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
   // diplomatic IOBinder should drive
   val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
   val clockGroupCombiner = ClockGroupCombiner()
-  val resetSynchronizer  = ClockGroupResetSynchronizer()
-  val tileClockGater     = if (prciParams.enableTileClockGating) { prci_ctrl_domain {
-    TileClockGater(prciParams.baseAddress + 0x00000, tlbus)
-  } } else { ClockGroupEphemeralNode() }
-  val tileResetSetter    = if (prciParams.enableTileResetSetting) { prci_ctrl_domain {
-    TileResetSetter(prciParams.baseAddress + 0x10000, tlbus, tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil)
-  } } else { ClockGroupEphemeralNode() }
+  val resetSynchronizer  = prci_ctrl_domain { ClockGroupResetSynchronizer() }
+  val tileClockGater     = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
+    val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
+    clock_gater.tlNode := prci_ctrl_bus
+    clock_gater
+  } }
+  val tileResetSetter    = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
+    val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
+      tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
+    reset_setter.tlNode := prci_ctrl_bus
+    reset_setter
+  } }
 
   (aggregator
     := frequencySpecifier
     := clockGroupCombiner
     := resetSynchronizer
-    := tileClockGater
-    := tileResetSetter
+    := tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
+    := tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
     := allClockGroupsNode)
 }
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
index bc722799..45f9374d 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
@@ -26,20 +26,26 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
     val sinks = clockNode.out.head._1.member.elements.toSeq
     require (sources.size == sinks.size)
     val nSinks = sinks.size
+    // The implicit clock of this module is the clock of the tilelink bus
+    // busReset is sync'd to that clock, and will be asserted longer than the
+    // resets coming in through the clockNode, since the busReset is derived from
+    // the clockNode resets in downstream PRCI nodes
+    val busReset = reset
 
     val regs = (0 until nSinks) .map { i =>
       val sinkName = sinks(i)._1
       val asyncReset = sources(i).reset
-      val reg = withReset (asyncReset) {
-        Module(new AsyncResetRegVec(w=divBits, init=0))
-      }
+      val reg = Module(new AsyncResetRegVec(w=divBits, init=0))
+
       println(s"${(address+i*4).toString(16)}: Clock domain $sinkName divider")
-      sinks(i)._2.clock := withClockAndReset(sources(i).clock, asyncReset) {
-        val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
-        divider.io.divisor := reg.io.q
-        divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
-        divider.io.clockOut
-      }
+      val divider = Module(new testchipip.ClockDivideOrPass(divBits, depth = 3, genClockGate = p(ClockGateImpl)))
+      divider.io.clockIn := sources(i).clock
+      // busReset is expected to be high for a long time, since reset will take a while to propagate
+      // to the TL bus. While reset is propagating, make sure we propagate a fast, undivided clock
+      // by setting divisor=0. The divisor signal into the ClockDividerOrPass is synchronized internally
+      divider.io.divisor := Mux(busReset.asBool, 0.U, reg.io.q)
+      divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
+      sinks(i)._2.clock := divider.io.clockOut
 
       // Note this is not synchronized to the output clock, which takes time to appear
       // so this is still asyncreset
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
index 23d525a6..b50ddd6d 100644
--- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -46,10 +46,3 @@ class TileClockGater(address: BigInt, beatBytes: Int)(implicit p: Parameters, va
   }
 }
 
-object TileClockGater {
-  def apply(address: BigInt, tlbus: TLBusWrapper)(implicit p: Parameters, v: ValName) = {
-    val gater = LazyModule(new TileClockGater(address, tlbus.beatBytes))
-    tlbus.toVariableWidthSlave(Some("clock-gater")) { gater.tlNode := TLBuffer() }
-    gater.clockNode
-  }
-}
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
index 9ea4bfd5..53dd36d0 100644
--- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -62,12 +62,3 @@ class TileResetSetter(address: BigInt, beatBytes: Int, tileNames: Seq[String], i
     }
   }
 }
-
-
-object TileResetSetter {
-  def apply(address: BigInt, tlbus: TLBusWrapper, tileNames: Seq[String], initResetHarts: Seq[Int])(implicit p: Parameters, v: ValName) = {
-    val setter = LazyModule(new TileResetSetter(address, tlbus.beatBytes, tileNames, initResetHarts))
-    tlbus.toVariableWidthSlave(Some("tile-reset-setter")) { setter.tlNode := TLBuffer() }
-    setter.clockNode
-  }
-}
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index 063b21d4..218b435c 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -48,7 +48,7 @@ class AbstractConfig extends Config(
 
   // By default, punch out IOs to the Harness
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"))) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++           // Default 500 MHz pbus
   new chipyard.config.WithMemoryBusFrequency(500.0) ++              // Default 500 MHz mbus
 
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index c85ef593..c8564a26 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -40,7 +40,7 @@ class ChipLikeRocketConfig extends Config(
   new chipyard.clocking.WithPLLSelectorDividerClockGenerator ++   // Use a PLL-based clock selector/divider generator structure
 
   // Create the uncore clock group
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"))) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("implicit", "sbus", "mbus", "cbus", "system_bus", "fbus", "pbus"), Nil)) ++
 
   new chipyard.config.AbstractConfig)
 
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 2bcc0089..099705e4 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -78,8 +78,8 @@ class MulticlockRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   // Frequency specifications
   new chipyard.config.WithTileFrequency(1000.0) ++        // Matches the maximum frequency of U540
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore"   , Seq("sbus", "cbus", "implicit")),
-                                                      ("periphery", Seq("pbus", "fbus"))) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore"   , Seq("sbus", "cbus", "implicit"), Nil),
+                                                      ("periphery", Seq("pbus", "fbus"), Nil)) ++
   new chipyard.config.WithSystemBusFrequency(500.0) ++    // Matches the maximum frequency of U540
   new chipyard.config.WithMemoryBusFrequency(500.0) ++    // Matches the maximum frequency of U540
   new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 20286fd6..ab00ad24 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -11,7 +11,7 @@ class AbstractTraceGenConfig extends Config(
   new chipyard.iobinders.WithAXI4MemPunchthrough ++
   new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
   new chipyard.clocking.WithPassthroughClockGenerator ++
-  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"))) ++
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
   new chipyard.config.WithTracegenSystem ++
   new chipyard.config.WithNoSubsystemDrivenClocks ++
   new chipyard.config.WithMemoryBusFrequency(1000.0) ++
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
index c10baab4..b960251d 100644
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -7,7 +7,7 @@ import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.prci._
 import freechips.rocketchip.util._
 import freechips.rocketchip.devices.debug.{ExportDebug, JtagDTMKey, Debug}
-import freechips.rocketchip.tilelink.{TLBuffer}
+import freechips.rocketchip.tilelink.{TLBuffer, TLFragmenter}
 import chipyard.{BuildSystem, DigitalTop}
 import chipyard.clocking._
 import chipyard.iobinders.{IOCellKey, JTAGChipIO}
@@ -33,9 +33,9 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule {
   val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
   val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }
 
-  tlbus.toVariableWidthSlave(Some("clock-div-ctrl")) { clockDivider.tlNode := TLBuffer() }
-  tlbus.toVariableWidthSlave(Some("clock-sel-ctrl")) { clockSelector.tlNode := TLBuffer() }
-  tlbus.toVariableWidthSlave(Some("pll-ctrl")) { pllCtrl.tlNode := TLBuffer() }
+  tlbus.coupleTo("clock-div-ctrl") { clockDivider.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
+  tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
+  tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
 
   system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
 
diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
index bf05ba9c..5e6c5d67 100644
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -165,17 +165,17 @@ trait CanHavePeripheryGCD { this: BaseSubsystem =>
     case Some(params) => {
       if (params.useAXI4) {
         val gcd = LazyModule(new GCDAXI4(params, pbus.beatBytes)(p))
-        pbus.toSlave(Some(portName)) {
+        pbus.coupleTo(portName) {
           gcd.node :=
           AXI4Buffer () :=
           TLToAXI4 () :=
           // toVariableWidthSlave doesn't use holdFirstDeny, which TLToAXI4() needsx
-          TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true)
+          TLFragmenter(pbus.beatBytes, pbus.blockBytes, holdFirstDeny = true) := _
         }
         Some(gcd)
       } else {
         val gcd = LazyModule(new GCDTL(params, pbus.beatBytes)(p))
-        pbus.toVariableWidthSlave(Some(portName)) { gcd.node }
+        pbus.coupleTo(portName) { gcd.node := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
         Some(gcd)
       }
     }
diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
index bb6ecd72..78237eca 100644
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -62,7 +62,7 @@ trait CanHavePeripheryInitZero { this: BaseSubsystem =>
 
   p(InitZeroKey) .map { k =>
     val initZero = LazyModule(new InitZero()(p))
-    fbus.fromPort(Some("init-zero"))() := initZero.node
+    fbus.coupleFrom("init-zero") { _ := initZero.node }
   }
 }
 
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 1a9114b9..38c8577a 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -67,6 +67,7 @@ case class MyCoreParams(
   val useCryptoNIST: Boolean = false
   val useCryptoSM: Boolean = false
   val traceHasWdata: Boolean = false
+  val useConditionalZero = false
 }
 
 // DOC include start: CanAttachTile
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index 15dfb992..3e315e65 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -203,7 +203,7 @@ trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
         genOut = FixedPoint(8.W, 3.BP),
         coeffs = Seq(1.F(0.BP), 2.F(0.BP), 3.F(0.BP)),
         params = params))
-      pbus.toVariableWidthSlave(Some("streamingFIR")) { streamingFIR.mem.get := TLFIFOFixer() }
+      pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
       Some(streamingFIR)
     }
     case None => None
diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
index 2846277c..45e05fc2 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -132,7 +132,7 @@ trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
   val passthrough = p(StreamingPassthroughKey) match {
     case Some(params) => {
       val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
-      pbus.toVariableWidthSlave(Some("streamingPassthrough")) { streamingPassthroughChain.mem.get := TLFIFOFixer() }
+      pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
       Some(streamingPassthroughChain)
     }
     case None => None
diff --git a/generators/cva6 b/generators/cva6
index 0011494b..46323fcd 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 0011494bb70d2327ab4d6b0258f5073f137927ee
+Subproject commit 46323fcd7407544c751b353f52e356eb8f33e9d1
diff --git a/generators/fft-generator b/generators/fft-generator
index be8ab768..f598d0c3 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit be8ab768bd15824c69531df632478e4429078b94
+Subproject commit f598d0c359c896e7853c8ef01c39ebecdd48b344
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index be016e6a..c20abca1 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -38,16 +38,22 @@ class FireSimClockBridgeInstantiator extends HarnessClockInstantiator {
 
     var instantiatedClocks = LinkedHashMap[Int, (Clock, Seq[String])]()
     // connect wires to clock source
-    for ((name, (freq, clock)) <- clockMap) {
-      val freqMHz = (freq / (1000 * 1000)).toInt
+    def findOrInstantiate(freqMHz: Int, name: String): Clock = {
       if (!instantiatedClocks.contains(freqMHz)) {
         val clock = Wire(Clock())
         instantiatedClocks(freqMHz) = (clock, Seq(name))
       } else {
         instantiatedClocks(freqMHz) = (instantiatedClocks(freqMHz)._1, instantiatedClocks(freqMHz)._2 :+ name)
       }
-      clock := instantiatedClocks(freqMHz)._1
+      instantiatedClocks(freqMHz)._1
     }
+    for ((name, (freq, clock)) <- clockMap) {
+      val freqMHz = (freq / (1000 * 1000)).toInt
+      clock := findOrInstantiate(freqMHz, name)
+    }
+
+    // The undivided reference clock as calculated by pllConfig must be instantiated
+    findOrInstantiate(pllConfig.referenceFreqMHz.toInt, "reference")
 
     val ratClocks = instantiatedClocks.map { case (freqMHz, (clock, names)) =>
       (RationalClock(names.mkString(","), 1, pllConfig.referenceFreqMHz.toInt / freqMHz), clock)
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index d2f8b994..c27abd50 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -103,11 +103,15 @@ class WithFireSimDesignTweaks extends Config(
 
 // Tweaks to modify target clock frequencies / crossings to legacy firesim defaults
 class WithFireSimHighPerfClocking extends Config(
+  // Create clock group for uncore that does not include mbus
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Nil)) ++
   // Optional: This sets the default frequency for all buses in the system to 3.2 GHz
   // (since unspecified bus frequencies will use the pbus frequency)
   // This frequency selection matches FireSim's legacy selection and is required
   // to support 200Gb NIC performance. You may select a smaller value.
   new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
+  new chipyard.config.WithSystemBusFrequency(3200.0) ++
+  new chipyard.config.WithFrontBusFrequency(3200.0) ++
   // Optional: These three configs put the DRAM memory system in it's own clock domain.
   // Removing the first config will result in the FASED timing model running
   // at the pbus freq (above, 3.2 GHz), which is outside the range of valid DDR3 speedgrades.
@@ -164,6 +168,23 @@ class WithFireSimHighPerfConfigTweaks extends Config(
   new WithFireSimDesignTweaks
 )
 
+// Tweak more representative of testchip configs
+class WithFireSimTestChipConfigTweaks extends Config(
+  // Frequency specifications
+  new chipyard.config.WithTileFrequency(1000.0) ++       // Realistic tile frequency for a test chip
+  new chipyard.config.WithSystemBusFrequency(500.0) ++   // Realistic system bus frequency
+  new chipyard.config.WithMemoryBusFrequency(1000.0) ++  // Needs to be 1000 MHz to model DDR performance accurately
+  new chipyard.config.WithPeripheryBusFrequency(500.0) ++  // Match the sbus and pbus frequency
+  new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "pbus", "fbus", "cbus", "implicit"), Seq("tile"))) ++
+  //  Crossing specifications
+  new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
+  new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
+  new freechips.rocketchip.subsystem.WithRationalRocketTiles ++   // Add rational crossings between RocketTile and uncore
+  new boom.common.WithRationalBoomTiles ++ // Add rational crossings between BoomTile and uncore
+  new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
+  new WithFireSimDesignTweaks
+)
+
 /*******************************************************************************
 * Full TARGET_CONFIG configurations. These set parameters of the target being
 * simulated.
diff --git a/generators/ibex b/generators/ibex
index 916fb7a6..66ec6e56 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 916fb7a6ff4a65f989279bcc082676a565beee0c
+Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc
diff --git a/generators/icenet b/generators/icenet
index ce1ec55c..68b4c7f3 160000
--- a/generators/icenet
+++ b/generators/icenet
@@ -1 +1 @@
-Subproject commit ce1ec55c1fd9c4339e7c0eec3a82d86041fa5d20
+Subproject commit 68b4c7f30f0119fe5cfab7ea99fb6927a563e112
diff --git a/generators/nvdla b/generators/nvdla
index 7130a5c0..730fad43 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 7130a5c0f7016cd177ec9cf908a18edd668660d1
+Subproject commit 730fad4360e67b14b1a4656ac58aaa40cfd4fe6b
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index c051956d..c1c809eb 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit c051956d3be3269c4ed9fcbb6afe920a6f54fd32
+Subproject commit c1c809ebd5c9a76cd60d8c3169cea4bf4b2fa8fd
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 25e2c635..47f7b714 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 25e2c63567689ebe1fc5e60fdfe3375a8dba071c
+Subproject commit 47f7b7144727f0340d511d35b9f6c7a91b2a276f
diff --git a/generators/sha3 b/generators/sha3
index 1fa5ef8a..b19b7c76 160000
--- a/generators/sha3
+++ b/generators/sha3
@@ -1 +1 @@
-Subproject commit 1fa5ef8ae5b67126d709193896e75dba50c5fd28
+Subproject commit b19b7c76fc865598b6a9806c8ef799064fc496ab
diff --git a/generators/testchipip b/generators/testchipip
index 456223c9..90401326 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 456223c9164596f7c57e114b69b2584e0dcf2901
+Subproject commit 904013261858f74140558522eaea2419dd466c79
diff --git a/project/plugins.sbt b/project/plugins.sbt
index 2425544f..36e1e8b6 100644
--- a/project/plugins.sbt
+++ b/project/plugins.sbt
@@ -1,3 +1,3 @@
-addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "2.1.1")
 addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.10.4")
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.3")
+addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.5.6")
diff --git a/scripts/repo-clean.sh b/scripts/repo-clean.sh
index 0ecdbb27..c966f265 100755
--- a/scripts/repo-clean.sh
+++ b/scripts/repo-clean.sh
@@ -26,10 +26,13 @@ rm -rf $RDIR/toolchains/esp-tools/riscv-tests/build.log
     popd
 )
 (
-    pushd $RDIR/generators/cva6/src/main/resources/vsrc
-    if [ -d cva6 ]
+    if [ -d $RDIR/generators/cva6/src/main/resources/cva6/vsrc ]
     then
-	git submodule deinit -f cva6
+        pushd $RDIR/generators/cva6/src/main/resources/cva6/vsrc
+        if [ -d cva6 ]
+        then
+	    git submodule deinit -f cva6
+        fi
+        popd
     fi
-    popd
 )
diff --git a/sims/firesim b/sims/firesim
index 966e0990..b0007729 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit 966e09907cde52f0ce68eb654bf6020b5b97a6c3
+Subproject commit b0007729905bb3be4125440924ecc97bed9ecf88
diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile
index fc0a9fdb..8517fc1d 100644
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -93,7 +93,7 @@ $(output_dir)/%.fsdb: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) $(sim_prefix)-* ucli.key
+	rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-* ucli.key
 
 clean-sim:
 	rm -rf $(model_dir) $(build_dir)/vc_hdrs.h $(sim) $(sim).daidir ucli.key
diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile
index dc556862..8cf51e23 100644
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -226,7 +226,7 @@ $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) $(sim_prefix)-*
+	rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
 
 clean-sim:
 	rm -rf $(model_dir) $(sim)
diff --git a/sims/xcelium/Makefile b/sims/xcelium/Makefile
index 2ca75d91..e37c12a1 100644
--- a/sims/xcelium/Makefile
+++ b/sims/xcelium/Makefile
@@ -77,7 +77,6 @@ XCELIUM_OPTS = $(XCELIUM_CC_OPTS) $(XCELIUM_NONCC_OPTS) $(PREPROC_DEFINES)
 model_dir = $(build_dir)/$(long_name)
 model_dir_debug = $(build_dir)/$(long_name).debug
 
-
 #########################################################################################
 # xcelium simulator rules
 #########################################################################################
@@ -87,37 +86,35 @@ $(sim_workdir): $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS)
 	$(XCELIUM) -elaborate $(XCELIUM_OPTS) $(EXTRA_SIM_SOURCES) $(XCELIUM_COMMON_ARGS)
 
 $(sim_run_tcl): $(sim_workdir)
-	echo "$$CAD_INFO_HEADER" > $(sim_run_tcl)
-	echo "run" >> $(sim_run_tcl)
-	echo "exit" >> $(sim_run_tcl)
+	echo "$$CAD_INFO_HEADER" > $@
+	echo "run" >> $@
+	echo "exit" >> $@
 
 # The system libstdc++ may not link correctly with some of our dynamic libs, so
 # force loading the conda one (if present) with LD_PRELOAD
 $(sim): $(sim_workdir) $(sim_run_tcl)
-	echo "#!/usr/bin/env bash" > $(sim)
-	echo "$$CAD_INFO_HEADER" >> $(sim)
-	cat arg-reshuffle >> $(sim)
-	echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim)
-	chmod +x $(sim)
+	echo "#!/usr/bin/env bash" > $@
+	echo "$$CAD_INFO_HEADER" >> $@
+	cat arg-reshuffle >> $@
+	echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
+	chmod +x $@
 
 $(sim_debug_run_tcl): $(sim_workdir)
-	echo "$$CAD_INFO_HEADER" > $(sim_debug_run_tcl)
-	echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $(sim_debug_run_tcl)
-	echo "set probe_packed_limit 64k" >> $(sim_debug_run_tcl)
-	echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $(sim_debug_run_tcl)
-	echo "run" >> $(sim_debug_run_tcl)
-	echo "database -close default_vcd_dump" >> $(sim_debug_run_tcl)
-	echo "exit" >> $(sim_debug_run_tcl)
-
+	echo "$$CAD_INFO_HEADER" > $@
+	echo "database -open default_vcd_dump -vcd -into \$$env(XCELIUM_WAVEFORM_FLAG)" >> $@
+	echo "set probe_packed_limit 64k" >> $@
+	echo "probe -create $(TB) -database default_vcd_dump -depth all -all" >> $@
+	echo "run" >> $@
+	echo "database -close default_vcd_dump" >> $@
+	echo "exit" >> $@
 
 $(sim_debug): $(sim_workdir) $(sim_debug_run_tcl)
-	echo "#!/usr/bin/env bash" > $(sim_debug)
-	echo "$$CAD_INFO_HEADER" >> $(sim_debug)
-	cat arg-reshuffle >> $(sim_debug)
-	echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $(sim_debug)
-	echo "LD_PRELOAD=$(base_dir)/.conda-env/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $(sim_debug)
-	chmod +x $(sim_debug)
-
+	echo "#!/usr/bin/env bash" > $@
+	echo "$$CAD_INFO_HEADER" >> $@
+	cat arg-reshuffle >> $@
+	echo "export XCELIUM_WAVEFORM_FLAG=\$$XCELIUM_WAVEFORM_FLAG" >> $@
+	echo "LD_PRELOAD=$(CONDA_PREFIX)/lib/libstdc++.so.6 $(XCELIUM) +permissive -R -input $(sim_debug_run_tcl) $(XCELIUM_COMMON_ARGS) +permissive-off \$$INPUT_ARGS" >> $@
+	chmod +x $@
 
 #########################################################################################
 # create vcd rules
@@ -131,7 +128,7 @@ $(output_dir)/%.vcd: $(output_dir)/% $(sim_debug)
 #########################################################################################
 .PHONY: clean clean-sim clean-sim-debug
 clean:
-	rm -rf $(gen_dir) $(sim_prefix)-*
+	rm -rf $(CLASSPATH_CACHE) $(gen_dir) $(sim_prefix)-*
 
 clean-sim:
 	rm -rf $(model_dir) $(sim) $(sim_workdir) $(sim_run_tcl) ucli.key bpad_*.err sigusrdump.out dramsim*.log
diff --git a/tools/barstools b/tools/barstools
index 30900965..fe81afec 160000
--- a/tools/barstools
+++ b/tools/barstools
@@ -1 +1 @@
-Subproject commit 30900965f0cc2d5046e2160dd9c700805a8e0542
+Subproject commit fe81afec14634316606a9dd10628c220d53bd256
diff --git a/variables.mk b/variables.mk
index f4e3d3c9..2beec438 100644
--- a/variables.mk
+++ b/variables.mk
@@ -8,7 +8,7 @@ HELP_COMPILATION_VARIABLES = \
 "   JAVA_TOOL_OPTIONS = if overridden, set underlying java tool options (default sets misc. sizes and tmp dir)" \
 "   SBT_OPTS          = set additional sbt command line options (these take the form -Dsbt.<option>=<setting>) " \
 "                       See https://www.scala-sbt.org/1.x/docs/Command-Line-Reference.html\#Command+Line+Options" \
-"   SBT_BIN           = if overridden, used to invoke sbt (default is to invoke sbt by sbt-launch.jar)" \
+"   SBT               = if overridden, used to invoke sbt (default is to invoke sbt by sbt-launch.jar)" \
 "   FIRRTL_LOGLEVEL   = if overridden, set firrtl log level (default is error)"
 
 HELP_PROJECT_VARIABLES = \
@@ -90,7 +90,7 @@ ifeq ($(SUB_PROJECT),hwacha)
 	TB                ?= TestDriver
 	TOP               ?= ExampleRocketSystem
 endif
-# For TestChipIP developers
+# For TestChipIP developers running unit-tests
 ifeq ($(SUB_PROJECT),testchipip)
 	SBT_PROJECT       ?= chipyard
 	MODEL             ?= TestHarness
@@ -102,6 +102,18 @@ ifeq ($(SUB_PROJECT),testchipip)
 	TB                ?= TestDriver
 	TOP               ?= UnitTestSuite
 endif
+# For rocketchip developers running unit-tests
+ifeq ($(SUB_PROJECT),rocketchip)
+	SBT_PROJECT       ?= chipyard
+	MODEL             ?= TestHarness
+	VLOG_MODEL        ?= $(MODEL)
+	MODEL_PACKAGE     ?= chipyard.unittest
+	CONFIG            ?= TLSimpleUnitTestConfig
+	CONFIG_PACKAGE    ?= freechips.rocketchip.unittest
+	GENERATOR_PACKAGE ?= chipyard
+	TB                ?= TestDriver
+	TOP               ?= UnitTestSuite
+endif
 # For IceNet developers
 ifeq ($(SUB_PROJECT),icenet)
 	SBT_PROJECT       ?= chipyard
@@ -146,6 +158,14 @@ ifeq ($(GENERATOR_PACKAGE),hwacha)
 	long_name=$(MODEL_PACKAGE).$(CONFIG)
 endif
 
+# classpaths
+CLASSPATH_CACHE ?= $(base_dir)/.classpath_cache
+CHIPYARD_CLASSPATH ?= $(CLASSPATH_CACHE)/chipyard.jar
+TAPEOUT_CLASSPATH ?= $(CLASSPATH_CACHE)/tapeout.jar
+# if *_CLASSPATH is a true java classpath, it can be colon-delimited list of paths (on *nix)
+CHIPYARD_CLASSPATH_TARGETS ?= $(subst :, ,$(CHIPYARD_CLASSPATH))
+TAPEOUT_CLASSPATH_TARGETS ?= $(subst :, ,$(TAPEOUT_CLASSPATH))
+
 # chisel generated outputs
 FIRRTL_FILE ?= $(build_dir)/$(long_name).fir
 ANNO_FILE   ?= $(build_dir)/$(long_name).anno.json
@@ -206,32 +226,37 @@ sim_common_files       ?= $(build_dir)/sim_files.common.f
 #########################################################################################
 JAVA_HEAP_SIZE ?= 8G
 JAVA_TMP_DIR ?= $(base_dir)/.java_tmp
-export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Dsbt.supershell=false -Djava.io.tmpdir=$(JAVA_TMP_DIR)
+export JAVA_TOOL_OPTIONS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -Djava.io.tmpdir=$(JAVA_TMP_DIR)
 
 #########################################################################################
 # default sbt launch command
 #########################################################################################
 SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)
 
-SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
-
-ifdef ENABLE_SBT_THIN_CLIENT
-SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
-# enabling speeds up sbt loading
-# use with sbt script or sbtn to bypass error code issues
-SBT_CLIENT_FLAG = --client
-endif
-
 # passes $(JAVA_TOOL_OPTIONS) from env to java
-export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always
-SBT_BIN ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
-SBT = $(SBT_BIN) $(SBT_CLIENT_FLAG)
-SBT_NON_THIN = $(subst $(SBT_CLIENT_FLAG),,$(SBT))
+export SBT_OPTS ?= -Dsbt.ivy.home=$(base_dir)/.ivy2 -Dsbt.global.base=$(base_dir)/.sbt -Dsbt.boot.directory=$(base_dir)/.sbt/boot/ -Dsbt.color=always -Dsbt.supershell=false -Dsbt.server.forcestart=true
+SBT ?= java -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS)
 
+# (1) - classpath of the fat jar
+# (2) - main class
+# (3) - main class arguments
+define run_jar_scala_main
+	cd $(base_dir) && java -cp $(1) $(2) $(3)
+endef
+
+# (1) - sbt project
+# (2) - main class
+# (3) - main class arguments
 define run_scala_main
 	cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
 endef
 
+# (1) - sbt project to assemble
+# (2) - classpath file(s) to create
+define run_sbt_assembly
+	cd $(base_dir) && $(SBT) ";project $(1); set assembly / assemblyOutputPath := file(\"$(2)\"); assembly"
+endef
+
 FIRRTL_LOGLEVEL ?= error
 
 #########################################################################################
diff --git a/vlsi/Makefile b/vlsi/Makefile
index 8ca74d31..b3901fe6 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -171,4 +171,4 @@ $(OBJ_DIR)/hammer.d: $(HAMMER_D_DEPS)
 #########################################################################################
 .PHONY: clean
 clean:
-	rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)
+	rm -rf $(VLSI_OBJ_DIR) hammer-vlsi*.log __pycache__ output.json $(GENERATED_CONFS) $(CLASSPATH_CACHE) $(gen_dir) $(SIM_CONF) $(SIM_DEBUG_CONF) $(SIM_TIMING_CONF) $(POWER_CONF)