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cat VLSI_RTL

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Harrison Liew
2023-02-28 13:10:49 -08:00
committed by GitHub
parent c1e8b20234
commit 89929cbb6e
1 changed files with 1 additions and 1 deletions
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vlsi/Makefile
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@@ -120,7 +120,7 @@ $(SYN_CONF): $(VLSI_RTL)
mkdir -p $(dir $@) mkdir -p $(dir $@)
echo "sim.inputs:" > $@ echo "sim.inputs:" > $@
echo " input_files:" >> $@ echo " input_files:" >> $@
for x in $(VLSI_RTL); do \ for x in $$(cat $(VLSI_RTL)); do \
echo ' - "'$$x'"' >> $@; \ echo ' - "'$$x'"' >> $@; \
done done
echo " input_files_meta: 'append'" >> $@ echo " input_files_meta: 'append'" >> $@