cat VLSI_RTL

2023-02-28 13:10:49 -08:00
parent c1e8b20234
commit 89929cbb6e
1 changed files with 1 additions and 1 deletions
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -120,7 +120,7 @@ $(SYN_CONF): $(VLSI_RTL)
 	mkdir -p $(dir $@)
 	echo "sim.inputs:" > $@
 	echo "  input_files:" >> $@
-	for x in $(VLSI_RTL); do \
+	for x in $$(cat $(VLSI_RTL)); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@