diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index e3845fe4..098879aa 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -27,7 +27,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with sifive.blocks.devices.spi.HasPeripherySPI // Enables optionally adding the sifive SPI port
 
 
-  with freechips.rocketchip.tilelink.CanHaveGPUTracer // Enable GPU Tracer
+  with freechips.rocketchip.tilelink.CanHaveMemtraceCore // Enable memtrace core
 
 
   with icenet.CanHavePeripheryIceNIC // Enables optionally adding the IceNIC for FireSim
diff --git a/generators/chipyard/src/main/scala/config/GPUConfig.scala b/generators/chipyard/src/main/scala/config/GPUConfig.scala
index 2f27dc89..8adeb0ff 100644
--- a/generators/chipyard/src/main/scala/config/GPUConfig.scala
+++ b/generators/chipyard/src/main/scala/config/GPUConfig.scala
@@ -3,20 +3,15 @@ package chipyard
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
 
-
-
-class GPUTracerConfig extends Config(
-
-  
-  // Attaching GPU Tracer to SBus
-  new freechips.rocketchip.tilelink.WithGPUTracer(4, "vecadd.core1.thread4.trace")++
-  
-
-  // Creating L2
+class MemtraceCoreConfig extends Config(
+  // Memtrace core
+  new freechips.rocketchip.tilelink.WithMemtraceCore("vecadd.core1.thread4.trace")++
+  new freechips.rocketchip.subsystem.WithNLanes(4) ++
+  // L2
   new freechips.rocketchip.subsystem.WithInclusiveCache(nWays=8, capacityKB=512) ++
   new freechips.rocketchip.subsystem.WithNBanks(4) ++                                   
   new chipyard.config.WithSystemBusWidth(64) ++ 
-  
+  // Small Rocket core that does nothing
   new freechips.rocketchip.subsystem.WithNCustomSmallCores(1) ++
   new chipyard.config.AbstractConfig
   )