wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Use require statement

Browse Source
This commit is contained in:
Edward Wang
2017-07-21 10:32:48 -07:00
committed by edwardcwang
parent 3cb424cf80
commit 80ca2e538f
2 changed files with 5 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
tapeout/src/main/scala/transforms/macros/Utils.scala
View File

@@ -18,9 +18,9 @@ class FirrtlMacroPort(port: MacroPort) {
val isWriter = !port.writeEnable.isEmpty && port.readEnable.isEmpty
val isReadWriter = !port.writeEnable.isEmpty && !port.readEnable.isEmpty
val AddrType = UIntType(IntWidth(ceilLog2(port.depth) max 1))
val DataType = UIntType(IntWidth(port.width))
val MaskType = UIntType(IntWidth(port.width / port.effectiveMaskGran))
val addrType = UIntType(IntWidth(ceilLog2(port.depth) max 1))
val dataType = UIntType(IntWidth(port.width))
val maskType = UIntType(IntWidth(port.width / port.effectiveMaskGran))
// Bundle representing this macro port.
val tpe = BundleType(Seq(