From 80ca2e538f5b43ef97c44807591a3009d4ee847f Mon Sep 17 00:00:00 2001 From: Edward Wang Date: Fri, 21 Jul 2017 10:32:48 -0700 Subject: [PATCH] Use require statement --- .../src/main/scala/transforms/macros/MacroCompiler.scala | 7 ++----- tapeout/src/main/scala/transforms/macros/Utils.scala | 6 +++--- 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala b/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala index 9112351e..46ac353c 100644 --- a/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala +++ b/tapeout/src/main/scala/transforms/macros/MacroCompiler.scala @@ -176,11 +176,8 @@ class MacroCompilerPass(mems: Option[Seq[Macro]], if (libPort.src.effectiveMaskGran == libPort.src.width) { bits(WRef(mem), low / memPort.src.effectiveMaskGran) } else { - if (libPort.src.effectiveMaskGran != 1) { - // TODO - System.err println "only single-bit mask supported" - return None - } + require(libPort.src.effectiveMaskGran == 1, "only single-bit mask supported for now") + cat(((low to high) map (i => bits(WRef(mem), i / memPort.src.effectiveMaskGran))).reverse) } case None => diff --git a/tapeout/src/main/scala/transforms/macros/Utils.scala b/tapeout/src/main/scala/transforms/macros/Utils.scala index 2355c9f3..49c6d07f 100644 --- a/tapeout/src/main/scala/transforms/macros/Utils.scala +++ b/tapeout/src/main/scala/transforms/macros/Utils.scala @@ -18,9 +18,9 @@ class FirrtlMacroPort(port: MacroPort) { val isWriter = !port.writeEnable.isEmpty && port.readEnable.isEmpty val isReadWriter = !port.writeEnable.isEmpty && !port.readEnable.isEmpty - val AddrType = UIntType(IntWidth(ceilLog2(port.depth) max 1)) - val DataType = UIntType(IntWidth(port.width)) - val MaskType = UIntType(IntWidth(port.width / port.effectiveMaskGran)) + val addrType = UIntType(IntWidth(ceilLog2(port.depth) max 1)) + val dataType = UIntType(IntWidth(port.width)) + val maskType = UIntType(IntWidth(port.width / port.effectiveMaskGran)) // Bundle representing this macro port. val tpe = BundleType(Seq(