Working up until the MMC attachment

2020-10-14 23:09:49 -07:00
parent dcac9b79df
commit 7f387a254b
7 changed files with 248 additions and 25 deletions
--- a/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/BringupGPIOs.scala
@@ -0,0 +1,28 @@
+package chipyard.fpga.vcu118.bringup
+
+import scala.collection.mutable.{LinkedHashMap}
+
+object BringupGPIOs {
+    // map of the pin name (akin to die pin name) to (fpga package pin, IOSTANDARD)
+    val pinMapping = LinkedHashMap(
+        // these connect to LEDs and switches on the VCU118 (and use 1.2V)
+        "led0"  -> ("AT32", "LVCMOS12"), // 0
+        "led1"  -> ("AV34", "LVCMOS12"), // 1
+        "led2"  -> ("AY30", "LVCMOS12"), // 2
+        "led3"  -> ("BB32", "LVCMOS12"), // 3
+        "led4"  -> ("BF32", "LVCMOS12"), // 4
+        "led5"  -> ("AU37", "LVCMOS12"), // 5
+        "led6"  -> ("AV36", "LVCMOS12"), // 6
+        "led7"  -> ("BA37", "LVCMOS12"), // 7
+        "sw0"   -> ("B17", "LVCMOS12"), // 8
+        "sw1"   -> ("G16", "LVCMOS12"), // 9
+        "sw2"   -> ("J16", "LVCMOS12"), // 10
+        "sw3"   -> ("D21", "LVCMOS12") // 11
+    )
+
+    // return list of names (ordered)
+    def names: Seq[String] = pinMapping.keys.toSeq
+
+    // return number of GPIOs
+    def width: Int = pinMapping.size
+}
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -0,0 +1,95 @@
+package chipyard.fpga.vcu118.bringup
+
+import math.min
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
+import freechips.rocketchip.system._
+import freechips.rocketchip.tile._
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.pwm._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.i2c._
+
+import sifive.fpgashells.shell.{DesignKey}
+import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD}
+
+import chipyard.{BuildTop}
+import chipyard.fpga.vcu118.bringup.{BringupGPIOs}
+
+import chipyard.harness._
+
+class WithBringupPeripherals extends Config((site, here, up) => {
+  case PeripheryUARTKey => List(
+    UARTParams(address = BigInt(0x64000000L)),
+    UARTParams(address = BigInt(0x64003000L)))
+  case PeripherySPIKey => List(
+    SPIParams(rAddress = BigInt(0x64001000L)),
+    SPIParams(rAddress = BigInt(0x64004000L)))
+  case VCU118ShellPMOD => "SDIO"
+  case PeripheryI2CKey => List(
+    I2CParams(address = BigInt(0x64005000L)))
+  case PeripheryGPIOKey => {
+    if (BringupGPIOs.width > 0) {
+      require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
+      val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000))
+      val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32)
+      List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => {
+        GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport))
+      })
+    }
+    else {
+      List.empty[GPIOParams]
+    }
+  }
+})
+
+class SmallModifications extends Config((site, here, up) => {
+  case SystemBusKey => up(SystemBusKey).copy(
+    errorDevice = Some(DevNullParams(
+      Seq(AddressSet(0x3000, 0xfff)),
+      maxAtomic=site(XLen)/8,
+      maxTransfer=128,
+      region = RegionType.TRACKED)))
+  case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency =
+    Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt),
+    errorDevice = None)
+  case DTSTimebase => BigInt(1000000)
+  case JtagDTMKey => new JtagDTMConfig(
+    idcodeVersion = 2,      // 1 was legacy (FE310-G000, Acai).
+    idcodePartNum = 0x000,  // Decided to simplify.
+    idcodeManufId = 0x489,  // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
+    debugIdleCycles = 5)    // Reasonable guess for synchronization
+})
+
+
+class FakeBringupConfig extends Config(
+  new WithBringupUART ++
+  new WithBringupSPI ++
+  new WithBringupI2C ++
+  new WithBringupGPIO ++
+  new WithBringupDDR ++
+  new WithUARTIOPassthrough ++
+  new WithSPIIOPassthrough ++
+  //new WithMMCSPIDTS ++
+  new WithI2CIOPassthrough ++
+  new WithGPIOIOPassthrough ++
+  new WithTLIOPassthrough ++
+  new WithBringupPeripherals ++
+  new chipyard.config.WithNoSubsystemDrivenClocks ++
+  new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
+  new chipyard.config.WithBootROM ++
+  new chipyard.config.WithL2TLBs(1024) ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
+  new freechips.rocketchip.subsystem.WithNoMMIOPort ++
+  new freechips.rocketchip.subsystem.WithNoSlavePort ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
+  new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
--- a/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/bringup/CustomOverlays.scala
@@ -0,0 +1,152 @@
+package chipyard.fpga.vcu118.bringup
+
+import chisel3._
+import chisel3.experimental.{attach}
+
+import freechips.rocketchip.diplomacy._
+import chipsalliance.rocketchip.config.{Parameters, Field}
+
+import sifive.fpgashells.shell._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell.xilinx._
+
+import sifive.blocks.devices.gpio._
+
+
+import chipyard.fpga.vcu118.{FMCPMap}
+
+/* Connect the I2C to certain FMC pins */
+class BringupI2CVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: I2CDesignInput, val shellInput: I2CShellInput)
+  extends I2CXilinxPlacedOverlay(name, designInput, shellInput)
+{
+  shell { InModuleBody {
+    require(shellInput.index == 0) // only support 1 I2C <-> FMC connection
+    val i2cLocations = List(List(FMCPMap("K11"), FMCPMap("E2")))
+    val packagePinsWithPackageIOs = Seq((i2cLocations(shellInput.index)(0), IOPin(io.scl)),
+                                        (i2cLocations(shellInput.index)(1), IOPin(io.sda)))
+
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      shell.xdc.addPackagePin(io, pin)
+      shell.xdc.addIOStandard(io, "LVCMOS18")
+      shell.xdc.addIOB(io)
+    } }
+  } }
+}
+
+class BringupI2CVCU118ShellPlacer(val shell: VCU118ShellBasicOverlays, val shellInput: I2CShellInput)(implicit val valName: ValName)
+  extends I2CShellPlacer[VCU118ShellBasicOverlays]
+{
+  def place(designInput: I2CDesignInput) = new BringupI2CVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
+}
+
+/* Connect the UART to certain FMC pins */
+class BringupUARTVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: UARTDesignInput, val shellInput: UARTShellInput)
+  extends UARTXilinxPlacedOverlay(name, designInput, shellInput, true)
+{
+  shell { InModuleBody {
+    val packagePinsWithPackageIOs = Seq((FMCPMap("E9"), IOPin(io.ctsn.get)), // unused
+                                        (FMCPMap("E10"), IOPin(io.rtsn.get)), // unused
+                                        (FMCPMap("C15"), IOPin(io.rxd)),
+                                        (FMCPMap("C14"), IOPin(io.txd)))
+
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      shell.xdc.addPackagePin(io, pin)
+      shell.xdc.addIOStandard(io, "LVCMOS18")
+      shell.xdc.addIOB(io)
+    } }
+
+    // add pullup on ctsn (ctsn is an input that is not used or driven)
+    packagePinsWithPackageIOs take 1 foreach { case (pin, io) => {
+      shell.xdc.addPullup(io)
+    } }
+  } }
+}
+
+class BringupUARTVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: UARTShellInput)(implicit val valName: ValName)
+  extends UARTShellPlacer[VCU118ShellBasicOverlays] {
+  def place(designInput: UARTDesignInput) = new BringupUARTVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
+}
+
+/* Connect SPI to ADI device */
+class BringupSPIVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: SPIDesignInput, val shellInput: SPIShellInput)
+   extends SDIOXilinxPlacedOverlay(name, designInput, shellInput)
+{
+  shell { InModuleBody {
+    val packagePinsWithPackageIOs = Seq((FMCPMap("H37"), IOPin(io.spi_clk)),
+                                        (FMCPMap("H19"), IOPin(io.spi_cs)),
+                                        (FMCPMap("H17"), IOPin(io.spi_dat(0))),
+                                        (FMCPMap("H28"), IOPin(io.spi_dat(1))),
+                                        (FMCPMap("H29"), IOPin(io.spi_dat(2))),
+                                        (FMCPMap("H16"), IOPin(io.spi_dat(3))))
+
+    packagePinsWithPackageIOs foreach { case (pin, io) => {
+      shell.xdc.addPackagePin(io, pin)
+      shell.xdc.addIOStandard(io, "LVCMOS18")
+    } }
+    packagePinsWithPackageIOs drop 1 foreach { case (pin, io) => {
+      shell.xdc.addPullup(io)
+      shell.xdc.addIOB(io)
+    } }
+  } }
+}
+
+class BringupSPIVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: SPIShellInput)(implicit val valName: ValName)
+  extends SPIShellPlacer[VCU118ShellBasicOverlays] {
+  def place(designInput: SPIDesignInput) = new BringupSPIVCU118PlacedOverlay(shell, valName.name, designInput, shellInput)
+}
+
+// TODO: Move this to a different location
+// SPI device description for ADI part
+class ADISPIDevice(spi: Device, maxMHz: Double = 1) extends SimpleDevice("clkgen", Seq("analog,adi9516-4")) {
+  override def parent = Some(spi)
+  override def describe(resources: ResourceBindings): Description = {
+    val Description(name, mapping) = super.describe(resources)
+    val extra = Map("spi-max-frequency" -> Seq(ResourceInt(maxMHz * 1000000)))
+    Description(name, mapping ++ extra)
+  }
+}
+
+/* Connect GPIOs to FMC */
+abstract class GPIOXilinxPlacedOverlay(name: String, di: GPIODesignInput, si: GPIOShellInput)
+  extends GPIOPlacedOverlay(name, di, si)
+{
+  def shell: XilinxShell
+
+  shell { InModuleBody {
+    (io.gpio zip tlgpioSink.bundle.pins).map { case (ioPin, sinkPin) =>
+      val iobuf = Module(new IOBUF)
+      iobuf.suggestName(s"gpio_iobuf")
+      attach(ioPin, iobuf.io.IO)
+      sinkPin.i.ival := iobuf.io.O
+      iobuf.io.T := !sinkPin.o.oe
+      iobuf.io.I := sinkPin.o.oval
+    }
+  } }
+}
+
+class BringupGPIOVCU118PlacedOverlay(val shell: VCU118ShellBasicOverlays, name: String, val designInput: GPIODesignInput, val shellInput: GPIOShellInput, gpioNames: Seq[String])
+   extends GPIOXilinxPlacedOverlay(name, designInput, shellInput)
+{
+  shell { InModuleBody {
+    require(gpioNames.length == io.gpio.length)
+
+    val packagePinsWithIOStdWithPackageIOs = (gpioNames zip io.gpio).map { case (name, io) =>
+      val (pin, iostd) = BringupGPIOs.pinMapping(name)
+      (pin, iostd, IOPin(io))
+    }
+
+    packagePinsWithIOStdWithPackageIOs foreach { case (pin, iostd, io) => {
+      shell.xdc.addPackagePin(io, pin)
+      shell.xdc.addIOStandard(io, iostd)
+      // TODO: no drive strength found
+      //if (iostd == "LVCMOS12") { shell.xdc.addDriveStrength(io, "8") }
+    } }
+  } }
+}
+
+class BringupGPIOVCU118ShellPlacer(shell: VCU118ShellBasicOverlays, val shellInput: GPIOShellInput, gpioNames: Seq[String])(implicit val valName: ValName)
+  extends GPIOShellPlacer[VCU118ShellBasicOverlays] {
+  def place(designInput: GPIODesignInput) = new BringupGPIOVCU118PlacedOverlay(shell, valName.name, designInput, shellInput, gpioNames)
+}
+
+
--- a/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala
@@ -0,0 +1,94 @@
+package chipyard.fpga.vcu118.bringup
+
+import chisel3._
+import chisel3.experimental.{Analog, IO}
+
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem}
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.util._
+
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell._
+import sifive.fpgashells.clocks._
+
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.i2c._
+import sifive.blocks.devices.gpio._
+
+import chipyard.fpga.vcu118.bringup.{BringupGPIOs, BringupUARTVCU118ShellPlacer, BringupSPIVCU118ShellPlacer, BringupI2CVCU118ShellPlacer, BringupGPIOVCU118ShellPlacer}
+import chipyard.{CanHaveMasterTLMemPort, HasHarnessSignalReferences}
+import chipyard.harness._
+
+/*** UART ***/
+class WithBringupUART extends OverrideHarnessBinder({
+  (system: HasPeripheryUARTModuleImp, th: HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
+    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
+      require(ports.size == 2)
+
+      vcu118th.outer.io_uart_bb.bundle <> ports.head
+      vcu118th.outer.io_uart_bb_2.bundle <> ports.last
+    } }
+
+    Nil
+  }
+})
+
+/*** SPI ***/
+class WithBringupSPI extends OverrideHarnessBinder({
+  (system: HasPeripherySPIModuleImp, th: HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
+    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
+      require(ports.size == 2)
+
+      vcu118th.outer.io_spi_bb.bundle <> ports.head
+      vcu118th.outer.io_spi_bb_2.bundle <> ports.last
+    } }
+
+    Nil
+  }
+})
+
+/*** I2C ***/
+class WithBringupI2C extends OverrideHarnessBinder({
+  (system: HasPeripheryI2CModuleImp, th: HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
+    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
+      require(ports.size == 1)
+
+      vcu118th.outer.io_i2c_bb.bundle <> ports.head
+    } }
+
+    Nil
+  }
+})
+
+/*** GPIO ***/
+class WithBringupGPIO extends OverrideHarnessBinder({
+  (system: HasPeripheryGPIOModuleImp, th: HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
+    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
+      (vcu118th.outer.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
+        bb_io.bundle <> dut_io
+      }
+    } }
+
+    Nil
+  }
+})
+
+/*** Experimental DDR ***/
+class WithBringupDDR extends OverrideHarnessBinder({
+  (system: CanHaveMasterTLMemPort, th: HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
+    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
+      require(ports.size == 1)
+
+      val bundles = vcu118th.outer.ddrClient.out.map(_._1)
+      val ddrClientBundle = Wire(new freechips.rocketchip.util.HeterogeneousBag(bundles.map(_.cloneType)))
+      bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+      ddrClientBundle <> ports.head
+    } }
+
+    Nil
+  }
+})
--- a/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
+++ b/fpga/src/main/scala/vcu118/bringup/IOBinders.scala
@@ -0,0 +1,90 @@
+package chipyard.fpga.vcu118.bringup
+
+import chisel3._
+import chisel3.util.experimental.{BoringUtils}
+import chisel3.experimental.{Analog, IO, DataMirror}
+
+import freechips.rocketchip.config._
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike, ResourceBinding, Resource, ResourceAddress}
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.jtag.{JTAGIO}
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.system.{SimAXIMem}
+import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4MasterNode, AXI4EdgeParameters}
+import freechips.rocketchip.util._
+import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
+import freechips.rocketchip.tilelink.{TLBundle}
+
+import sifive.blocks.devices.gpio._
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.i2c._
+import tracegen.{TraceGenSystemModuleImp}
+
+import barstools.iocell.chisel._
+
+import testchipip._
+import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
+
+import chipyard.{GlobalResetSchemeKey, CanHaveMasterTLMemPort}
+import chipyard.iobinders.{OverrideIOBinder}
+
+class WithUARTIOPassthrough extends OverrideIOBinder({
+  (system: HasPeripheryUARTModuleImp) => {
+    val io_uart_pins_temp = system.uart.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"uart_$i") }
+    (io_uart_pins_temp zip system.uart).map { case (io, sysio) =>
+      io <> sysio
+    }
+    (io_uart_pins_temp, Nil)
+  }
+})
+
+class WithGPIOIOPassthrough extends OverrideIOBinder({
+  (system: HasPeripheryGPIOModuleImp) => {
+    val io_gpio_pins_temp = system.gpio.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"gpio_$i") }
+    (io_gpio_pins_temp zip system.gpio).map { case (io, sysio) =>
+      io <> sysio
+    }
+    (io_gpio_pins_temp, Nil)
+  }
+})
+
+class WithSPIIOPassthrough extends OverrideIOBinder({
+  (system: HasPeripherySPIModuleImp) => {
+    val io_spi_pins_temp = system.spi.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"spi_$i") }
+    (io_spi_pins_temp zip system.spi).map { case (io, sysio) =>
+      io <> sysio
+    }
+    (io_spi_pins_temp, Nil)
+  }
+})
+
+//class WithMMCSPIDTS extends OverrideIOBinder({
+//  (system: HasPeripherySPI) => {
+//
+//    val mmcDev = new MMCDevice(system.tlspi.head.device, 1)
+//    ResourceBinding {
+//      Resource(mmcDev, "reg").bind(ResourceAddress(0))
+//    }
+//
+//    (Nil, Nil)
+//  }
+//})
+
+class WithI2CIOPassthrough extends OverrideIOBinder({
+  (system: HasPeripheryI2CModuleImp) => {
+    val io_i2c_pins_temp = system.i2c.zipWithIndex.map { case (dio, i) => IO(dio.cloneType).suggestName(s"i2c_$i") }
+    (io_i2c_pins_temp zip system.i2c).map { case (io, sysio) =>
+      io <> sysio
+    }
+    (io_i2c_pins_temp, Nil)
+  }
+})
+
+class WithTLIOPassthrough extends OverrideIOBinder({
+  (system: CanHaveMasterTLMemPort) => {
+    val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
+    io_tl_mem_pins_temp <> system.mem_tl
+    (Seq(io_tl_mem_pins_temp), Nil)
+  }
+})
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -0,0 +1,189 @@
+package chipyard.fpga.vcu118.bringup
+
+import chisel3._
+import chisel3.experimental.{Analog, IO}
+
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.subsystem.{ExtMem, BaseSubsystem}
+import freechips.rocketchip.tilelink._
+
+import sifive.fpgashells.shell.xilinx._
+import sifive.fpgashells.ip.xilinx._
+import sifive.fpgashells.shell._
+import sifive.fpgashells.clocks._
+
+import sifive.blocks.devices.uart._
+import sifive.blocks.devices.spi._
+import sifive.blocks.devices.i2c._
+import sifive.blocks.devices.gpio._
+
+import chipyard.harness._
+import chipyard.{HasHarnessSignalReferences, HasTestHarnessFunctions, BuildTop, CanHaveMasterTLMemPort, ChipTop}
+
+case object DUTFrequencyKey extends Field[Double](100.0)
+
+class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118ShellBasicOverlays {
+
+  def dp = designParameters
+
+  val pmod_is_sdio  = p(VCU118ShellPMOD) == "SDIO"
+  val jtag_location = Some(if (pmod_is_sdio) "FMC_J2" else "PMOD_J52")
+
+  // Order matters; ddr depends on sys_clock
+  val uart      = Overlay(UARTOverlayKey, new UARTVCU118ShellPlacer(this, UARTShellInput()))
+  val sdio      = if (pmod_is_sdio) Some(Overlay(SPIOverlayKey, new SDIOVCU118ShellPlacer(this, SPIShellInput()))) else None
+  val jtag      = Overlay(JTAGDebugOverlayKey, new JTAGDebugVCU118ShellPlacer(this, JTAGDebugShellInput(location = jtag_location)))
+  val cjtag     = Overlay(cJTAGDebugOverlayKey, new cJTAGDebugVCU118ShellPlacer(this, cJTAGDebugShellInput()))
+  val jtagBScan = Overlay(JTAGDebugBScanOverlayKey, new JTAGDebugBScanVCU118ShellPlacer(this, JTAGDebugBScanShellInput()))
+  val fmc       = Overlay(PCIeOverlayKey, new PCIeVCU118FMCShellPlacer(this, PCIeShellInput()))
+  val edge      = Overlay(PCIeOverlayKey, new PCIeVCU118EdgeShellPlacer(this, PCIeShellInput()))
+
+  val topDesign = LazyModule(p(BuildTop)(dp))
+
+  // place all clocks in the shell
+  dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) }
+
+  /*** Connect/Generate clocks ***/
+
+  // connect to the PLL that will generate multiple clocks
+  val harnessSysPLL = dp(PLLFactoryKey)()
+  sys_clock.get() match {
+    case Some(x : SysClockVCU118PlacedOverlay) => {
+      harnessSysPLL := x.node
+    }
+  }
+
+  // create and connect to the dutClock
+  val dutClock = ClockSinkNode(freqMHz = dp(DUTFrequencyKey))
+  val dutWrangler = LazyModule(new ResetWrangler)
+  val dutGroup = ClockGroup()
+  dutClock := dutWrangler.node := dutGroup := harnessSysPLL
+
+  //InModuleBody {
+  //  topDesign.module match { case td: LazyModuleImp => {
+  //      td.clock := dutClock.in.head._1.clock
+  //      td.reset := dutClock.in.head._1.reset
+  //    }
+  //  }
+  //}
+
+  // connect ref clock to dummy sink node
+  ref_clock.get() match {
+    case Some(x : RefClockVCU118PlacedOverlay) => {
+      val sink = ClockSinkNode(Seq(ClockSinkParameters()))
+      sink := x.node
+    }
+  }
+
+    // extra overlays
+
+  /*** UART ***/
+
+  require(dp(PeripheryUARTKey).size == 2)
+
+  // 1st UART goes to the VCU118 dedicated UART
+
+  // BundleBridgeSource is a was for Diplomacy to connect something from very deep in the design
+  // to somewhere much, much higher. For ex. tunneling trace from the tile to the very top level.
+  val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
+  dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
+
+  // 2nd UART goes to the FMC UART
+
+  val uart_fmc = Overlay(UARTOverlayKey, new BringupUARTVCU118ShellPlacer(this, UARTShellInput()))
+
+  val io_uart_bb_2 = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).last)))
+  dp(UARTOverlayKey).last.place(UARTDesignInput(io_uart_bb_2))
+
+  /*** SPI ***/
+
+  require(dp(PeripherySPIKey).size == 2)
+
+  // 1st SPI goes to the VCU118 SDIO port
+
+  val io_spi_bb = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).head)))
+  val sdio_placed = dp(SPIOverlayKey).head.place(SPIDesignInput(dp(PeripherySPIKey).head, io_spi_bb))
+
+  // 2nd SPI goes to the ADI port
+
+  val adi = Overlay(SPIOverlayKey, new BringupSPIVCU118ShellPlacer(this, SPIShellInput()))
+
+  val io_spi_bb_2 = BundleBridgeSource(() => (new SPIPortIO(dp(PeripherySPIKey).last)))
+  val adi_placed = dp(SPIOverlayKey).last.place(SPIDesignInput(dp(PeripherySPIKey).last, io_spi_bb_2))
+
+  /*** I2C ***/
+
+  val i2c = Overlay(I2COverlayKey, new BringupI2CVCU118ShellPlacer(this, I2CShellInput()))
+
+  val io_i2c_bb = BundleBridgeSource(() => (new I2CPort))
+  dp(I2COverlayKey).head.place(I2CDesignInput(io_i2c_bb))
+
+  /*** GPIO ***/
+
+  val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
+    val maxGPIOSupport = 32
+    val names = BringupGPIOs.names.slice(maxGPIOSupport*i, maxGPIOSupport*(i+1))
+    Overlay(GPIOOverlayKey, new BringupGPIOVCU118ShellPlacer(this, GPIOShellInput(), names))
+  })
+
+  val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
+  (dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
+    placer.place(GPIODesignInput(params, io_gpio_bb(i)))
+  }
+
+  /*** DDR ***/
+
+  val ddrWrangler = LazyModule(new ResetWrangler)
+  val ddrPlaced = dp(DDROverlayKey).head.place(DDRDesignInput(dp(ExtMem).get.master.base, ddrWrangler.node, harnessSysPLL))
+
+  // connect 1 mem. channel to the FPGA DDR
+  val inParams = topDesign match { case td: ChipTop =>
+    td.lazySystem match { case lsys: CanHaveMasterTLMemPort =>
+      lsys.memTLNode.edges.in(0)
+    }
+  }
+  val ddrClient = TLClientNode(Seq(inParams.master))
+  ddrPlaced.overlayOutput.ddr := ddrClient
+
+  // module implementation
+  override lazy val module = new BringupVCU118FPGATestHarnessImp(this)
+}
+
+class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
+
+  val outer = _outer
+
+  val reset = IO(Input(Bool()))
+  _outer.xdc.addPackagePin(reset, "L19")
+  _outer.xdc.addIOStandard(reset, "LVCMOS12")
+
+  val reset_ibuf = Module(new IBUF)
+  reset_ibuf.io.I := reset
+
+  val sysclk: Clock = _outer.sys_clock.get() match {
+    case Some(x: SysClockVCU118PlacedOverlay) => x.clock
+  }
+
+  val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
+  _outer.sdc.addAsyncPath(Seq(powerOnReset))
+
+  val ereset: Bool = _outer.chiplink.get() match {
+    case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n
+    case _ => false.B
+  }
+
+  _outer.pllReset := (reset_ibuf.io.O || powerOnReset || ereset)
+
+  // cy stuff
+  val harnessClock = _outer.dutClock.in.head._1.clock
+  val harnessReset = WireInit(_outer.dutClock.in.head._1.reset)
+  val dutReset = harnessReset
+  val success = false.B
+
+  // harness binders are non-lazy
+  _outer.topDesign match { case d: HasTestHarnessFunctions =>
+    d.harnessFunctions.foreach(_(this))
+    ApplyHarnessBinders(this, d.lazySystem, p(HarnessBinders), d.portMap.toMap)
+  }
+}