96 lines
3.6 KiB
Scala
96 lines
3.6 KiB
Scala
package chipyard.fpga.vcu118.bringup
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import math.min
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import freechips.rocketchip.config._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.devices.debug._
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import freechips.rocketchip.devices.tilelink._
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import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
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import freechips.rocketchip.system._
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import freechips.rocketchip.tile._
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import sifive.blocks.devices.gpio._
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import sifive.blocks.devices.pwm._
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import sifive.blocks.devices.spi._
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import sifive.blocks.devices.uart._
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import sifive.blocks.devices.i2c._
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import sifive.fpgashells.shell.{DesignKey}
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import sifive.fpgashells.shell.xilinx.{VCU118ShellPMOD}
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import chipyard.{BuildTop}
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import chipyard.fpga.vcu118.bringup.{BringupGPIOs}
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import chipyard.harness._
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class WithBringupPeripherals extends Config((site, here, up) => {
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case PeripheryUARTKey => List(
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UARTParams(address = BigInt(0x64000000L)),
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UARTParams(address = BigInt(0x64003000L)))
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case PeripherySPIKey => List(
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SPIParams(rAddress = BigInt(0x64001000L)),
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SPIParams(rAddress = BigInt(0x64004000L)))
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case VCU118ShellPMOD => "SDIO"
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case PeripheryI2CKey => List(
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I2CParams(address = BigInt(0x64005000L)))
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case PeripheryGPIOKey => {
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if (BringupGPIOs.width > 0) {
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require(BringupGPIOs.width <= 64) // currently only support 64 GPIOs (change addrs to get more)
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val gpioAddrs = Seq(BigInt(0x64002000), BigInt(0x64007000))
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val maxGPIOSupport = 32 // max gpios supported by SiFive driver (split by 32)
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List.tabulate(((BringupGPIOs.width - 1)/maxGPIOSupport) + 1)(n => {
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GPIOParams(address = gpioAddrs(n), width = min(BringupGPIOs.width - maxGPIOSupport*n, maxGPIOSupport))
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})
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}
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else {
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List.empty[GPIOParams]
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}
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}
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})
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class SmallModifications extends Config((site, here, up) => {
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case SystemBusKey => up(SystemBusKey).copy(
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errorDevice = Some(DevNullParams(
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Seq(AddressSet(0x3000, 0xfff)),
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maxAtomic=site(XLen)/8,
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maxTransfer=128,
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region = RegionType.TRACKED)))
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case PeripheryBusKey => up(PeripheryBusKey, site).copy(dtsFrequency =
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Some(BigDecimal(site(DUTFrequencyKey)*1000000).setScale(0, BigDecimal.RoundingMode.HALF_UP).toBigInt),
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errorDevice = None)
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case DTSTimebase => BigInt(1000000)
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case JtagDTMKey => new JtagDTMConfig(
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idcodeVersion = 2, // 1 was legacy (FE310-G000, Acai).
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idcodePartNum = 0x000, // Decided to simplify.
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idcodeManufId = 0x489, // As Assigned by JEDEC to SiFive. Only used in wrappers / test harnesses.
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debugIdleCycles = 5) // Reasonable guess for synchronization
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})
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class FakeBringupConfig extends Config(
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new WithBringupUART ++
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new WithBringupSPI ++
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new WithBringupI2C ++
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new WithBringupGPIO ++
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new WithBringupDDR ++
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new WithUARTIOPassthrough ++
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new WithSPIIOPassthrough ++
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//new WithMMCSPIDTS ++
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new WithI2CIOPassthrough ++
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new WithGPIOIOPassthrough ++
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new WithTLIOPassthrough ++
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new WithBringupPeripherals ++
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new chipyard.config.WithNoSubsystemDrivenClocks ++
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new chipyard.config.WithPeripheryBusFrequencyAsDefault ++
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new chipyard.config.WithBootROM ++
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new chipyard.config.WithL2TLBs(1024) ++
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++
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new freechips.rocketchip.subsystem.WithNoSlavePort ++
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new freechips.rocketchip.subsystem.WithInclusiveCache ++
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.system.BaseConfig)
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