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[firechip] Update scalatest suite

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This commit is contained in:
David Biancolin
2019-10-04 18:15:34 +00:00
parent 5845862525
commit 7c0bb51242
1 changed files with 3 additions and 3 deletions
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6
generators/firechip/src/test/scala/ScalaTestSuite.scala
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@@ -130,9 +130,9 @@ abstract class FireSimTestSuite(
runSuite("verilator")(FastBlockdevTests) runSuite("verilator")(FastBlockdevTests)
} }
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipQuadCoreConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") { class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
runSuite("verilator")(NICLoopbackTests) runSuite("verilator")(NICLoopbackTests)
} }
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")