From 7c0bb51242e1a9915c16934edfbdd886537c9fb1 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 18:15:34 +0000 Subject: [PATCH] [firechip] Update scalatest suite --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 49737be4..e7194d8c 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -130,9 +130,9 @@ abstract class FireSimTestSuite( runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipQuadCoreConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") -class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") { +class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")