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bump down to innovus 18.1

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This commit is contained in:
Harrison Liew
2019-10-02 00:34:29 -07:00
parent b6400cbb0c
commit 7a39cbdddc
7 changed files with 341 additions and 342 deletions
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5
docs/VLSI/Tutorial.rst
View File

@@ -54,8 +54,9 @@ Prerequisites
* Genus, Innovus, and Calibre licenses
* For ASAP7 specifically:
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory.
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion.
* Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded).
Initial Setup
-------------
@@ -83,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u
make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead.
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches.
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.

4
vlsi/example-vlsi
View File

@@ -36,9 +36,7 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
set fp [open "{script_file}" "w"]
puts -nonewline $fp "{script_text}"
close $fp
if {{ [catch {{ exec python3 {script_file} }} msg] }} {{
puts "$::errorInfo"
}}
exec python3 {script_file}
'''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py")))
return True

2
vlsi/example.yml
View File

@@ -124,7 +124,7 @@ synthesis.genus.version: "1813"
vlsi.core.par_tool: "innovus"
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
vlsi.core.par_tool_path_meta: "append"
par.innovus.version: "191"
par.innovus.version: "181"
par.innovus.design_flow_effort: "standard"
par.inputs.gds_merge: true
# Calibre options

BIN
vlsi/extra_libraries/example/ExampleDCO.gds
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Binary file not shown.

668
vlsi/extra_libraries/example/ExampleDCO.lef
View File

@@ -6,374 +6,374 @@ MACRO ExampleDCO
CLASS BLOCK ;
ORIGIN 0 0 ;
FOREIGN ExampleDCO 0 0 ;
SIZE 128.0 BY 128.0 ;
SIZE 129.536 BY 125.536 ;
SYMMETRY X Y ;
PIN VDD
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER M7 ;
RECT 32.96 124.0 33.6 128.0 ;
END
PORT
LAYER M5 ;
RECT 10.608 121.536 11.088 125.536 ;
END
END VDD
PIN VSS
DIRECTION INOUT ;
USE GROUND ;
PORT
PORT
LAYER M5 ;
RECT 93.12 124.0 93.76 128.0 ;
END
RECT 11.712 121.536 12.192 125.536 ;
END
END VSS
PIN col_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 113.28 4.0 113.664 ;
END
END col_sel_b[13]
PIN col_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 107.648 4.0 108.032 ;
END
END col_sel_b[11]
PIN col_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 90.752 4.0 91.136 ;
END
END col_sel_b[5]
PIN col_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 110.464 4.0 110.848 ;
END
END col_sel_b[12]
PIN col_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 104.832 4.0 105.216 ;
END
END col_sel_b[10]
PIN col_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 102.016 4.0 102.4 ;
END
END col_sel_b[9]
PIN col_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 99.2 4.0 99.584 ;
END
END col_sel_b[8]
PIN col_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 96.384 4.0 96.768 ;
END
END col_sel_b[7]
PIN col_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 93.568 4.0 93.952 ;
END
END col_sel_b[6]
PIN col_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 87.936 4.0 88.32 ;
END
END col_sel_b[4]
PIN col_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 85.12 4.0 85.504 ;
END
END col_sel_b[3]
PIN col_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 82.304 4.0 82.688 ;
END
END col_sel_b[2]
PIN col_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 79.488 4.0 79.872 ;
END
END col_sel_b[1]
PIN col_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 76.672 4.0 77.056 ;
END
END col_sel_b[0]
PIN row_sel_b[14]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 71.04 4.0 71.424 ;
END
END row_sel_b[14]
PIN row_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 68.224 4.0 68.608 ;
END
END row_sel_b[13]
PIN row_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 65.408 4.0 65.792 ;
END
END row_sel_b[12]
PIN row_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 62.592 4.0 62.976 ;
END
END row_sel_b[11]
PIN row_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 59.776 4.0 60.16 ;
END
END row_sel_b[10]
PIN row_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 56.96 4.0 57.344 ;
END
END row_sel_b[9]
PIN row_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 54.144 4.0 54.528 ;
END
END row_sel_b[8]
PIN row_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 51.328 4.0 51.712 ;
END
END row_sel_b[7]
PIN row_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 48.512 4.0 48.896 ;
END
END row_sel_b[6]
PIN row_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 45.696 4.0 46.08 ;
END
END row_sel_b[5]
PIN row_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 42.88 4.0 43.264 ;
END
END row_sel_b[4]
PIN row_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 40.064 4.0 40.448 ;
END
END row_sel_b[3]
PIN row_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 37.248 4.0 37.632 ;
END
END row_sel_b[2]
PIN row_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 34.432 4.0 34.816 ;
END
END row_sel_b[1]
PIN row_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 31.616 4.0 32.0 ;
END
END row_sel_b[0]
PIN code_regulator[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 28.8 4.0 29.184 ;
END
END code_regulator[7]
PIN code_regulator[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 25.984 4.0 26.368 ;
END
END code_regulator[6]
PIN code_regulator[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 23.168 4.0 23.552 ;
END
END code_regulator[5]
PIN code_regulator[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 20.352 4.0 20.736 ;
END
END code_regulator[4]
PIN code_regulator[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 17.536 4.0 17.92 ;
END
END code_regulator[3]
PIN code_regulator[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 14.72 4.0 15.104 ;
END
END code_regulator[2]
PIN code_regulator[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 11.904 4.0 12.288 ;
END
END code_regulator[1]
PIN code_regulator[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 9.088 4.0 9.472 ;
END
END code_regulator[0]
PIN row_sel_b[15]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 73.856 4.0 74.24 ;
END
END row_sel_b[15]
PIN dither
DIRECTION INPUT ;
USE SIGNAL ;
PORT
PORT
LAYER M4 ;
RECT 0.0 6.272 4.0 6.656 ;
END
RECT 0.0 0.384 4.0 0.768 ;
END
END dither
PIN row_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 1.536 4.0 1.92 ;
END
END row_sel_b[0]
PIN row_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 2.688 4.0 3.072 ;
END
END row_sel_b[1]
PIN row_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 3.84 4.0 4.224 ;
END
END row_sel_b[2]
PIN row_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 4.992 4.0 5.376 ;
END
END row_sel_b[3]
PIN row_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 6.144 4.0 6.528 ;
END
END row_sel_b[4]
PIN row_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 7.296 4.0 7.68 ;
END
END row_sel_b[5]
PIN row_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 8.448 4.0 8.832 ;
END
END row_sel_b[6]
PIN row_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 9.6 4.0 9.984 ;
END
END row_sel_b[7]
PIN row_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 10.752 4.0 11.136 ;
END
END row_sel_b[8]
PIN row_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 11.904 4.0 12.288 ;
END
END row_sel_b[9]
PIN row_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 13.056 4.0 13.44 ;
END
END row_sel_b[10]
PIN row_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 14.208 4.0 14.592 ;
END
END row_sel_b[11]
PIN row_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 15.36 4.0 15.744 ;
END
END row_sel_b[12]
PIN row_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 16.512 4.0 16.896 ;
END
END row_sel_b[13]
PIN row_sel_b[14]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 17.664 4.0 18.048 ;
END
END row_sel_b[14]
PIN row_sel_b[15]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 18.816 4.0 19.2 ;
END
END row_sel_b[15]
PIN col_sel_b[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 19.968 4.0 20.352 ;
END
END col_sel_b[0]
PIN col_sel_b[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 21.12 4.0 21.504 ;
END
END col_sel_b[1]
PIN col_sel_b[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 22.272 4.0 22.656 ;
END
END col_sel_b[2]
PIN col_sel_b[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 23.424 4.0 23.808 ;
END
END col_sel_b[3]
PIN col_sel_b[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 24.576 4.0 24.96 ;
END
END col_sel_b[4]
PIN col_sel_b[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 25.728 4.0 26.112 ;
END
END col_sel_b[5]
PIN col_sel_b[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 26.88 4.0 27.264 ;
END
END col_sel_b[6]
PIN col_sel_b[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 28.032 4.0 28.416 ;
END
END col_sel_b[7]
PIN col_sel_b[8]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 29.184 4.0 29.568 ;
END
END col_sel_b[8]
PIN col_sel_b[9]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 30.336 4.0 30.72 ;
END
END col_sel_b[9]
PIN col_sel_b[10]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 31.488 4.0 31.872 ;
END
END col_sel_b[10]
PIN col_sel_b[11]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 32.64 4.0 33.024 ;
END
END col_sel_b[11]
PIN col_sel_b[12]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 33.792 4.0 34.176 ;
END
END col_sel_b[12]
PIN col_sel_b[13]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 34.944 4.0 35.328 ;
END
END col_sel_b[13]
PIN code_regulator[0]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 36.096 4.0 36.48 ;
END
END code_regulator[0]
PIN code_regulator[1]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 37.248 4.0 37.632 ;
END
END code_regulator[1]
PIN code_regulator[2]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 38.4 4.0 38.784 ;
END
END code_regulator[2]
PIN code_regulator[3]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 39.552 4.0 39.936 ;
END
END code_regulator[3]
PIN code_regulator[4]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 40.704 4.0 41.088 ;
END
END code_regulator[4]
PIN code_regulator[5]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 41.856 4.0 42.24 ;
END
END code_regulator[5]
PIN code_regulator[6]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 43.008 4.0 43.392 ;
END
END code_regulator[6]
PIN code_regulator[7]
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M4 ;
RECT 0.0 44.16 4.0 44.544 ;
END
END code_regulator[7]
PIN sleep_b
DIRECTION INPUT ;
USE SIGNAL ;
PORT
LAYER M5 ;
RECT 9.792 0.0 10.176 4.0 ;
END
PORT
LAYER M4 ;
RECT 0.0 45.312 4.0 45.696 ;
END
END sleep_b
PIN clock
DIRECTION OUTPUT ;
USE SIGNAL ;
PORT
PORT
LAYER M4 ;
RECT 124.0 70.864 128.0 71.248 ;
END
RECT 125.536 0.384 129.536 0.768 ;
END
END clock
OBS
OBS
LAYER M1 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M2 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M3 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M4 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M5 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M6 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M7 ;
RECT 4.0 4.0 124.0 124.0 ;
RECT 4.0 0.0 125.536 121.536 ;
LAYER M8 ;
RECT 0.0 0.0 128.0 128.0 ;
RECT 0.0 0.0 129.536 121.536 ;
LAYER M9 ;
RECT 0.0 0.0 128.0 128.0 ;
RECT 0.0 0.0 129.536 121.536 ;
LAYER Pad ;
RECT 0.0 0.0 128.0 128.0 ;
END
RECT 0.0 0.0 129.536 121.536 ;
END
END ExampleDCO
END LIBRARY

2
vlsi/hammer

Submodule vlsi/hammer updated: 1b07b9a378...8822681524

2
vlsi/hammer-cadence-plugins

Submodule vlsi/hammer-cadence-plugins updated: 06ce365b36...5e93f2e72f