Merge branch 'openroad' of https://github.com/ucb-bar/chipyard into openroad

2023-03-13 11:27:47 -07:00
parent f2cf6b7e18 dfc01a2d0f
commit 78b6bdb754
21 changed files with 759 additions and 1277 deletions
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -107,6 +107,65 @@ jobs:
          source env.sh
          cd sims/verilator
          make verilog
+      - name: VLSI test
+        run: |
+          cd ${{ env.REMOTE_WORK_DIR }}
+          eval "$(conda shell.bash hook)"
+          source env.sh
+
+          cd vlsi
+
+          # NOTE: most conda installs are in separate conda envs because they mess up 
+          #   each other's versions (for no apparent reason) and we need the latest versions
+          conda config --add channels defaults
+          conda config --add channels litex-hub
+
+          # installs for example-sky130.yml
+          conda create -y --prefix ./.conda-sky130 open_pdks.sky130a=1.0.399_0_g63dbde9
+          git clone https://github.com/rahulk29/sram22_sky130_macros.git
+
+          # installs for example-openroad.yml
+          conda create -y --prefix ./.conda-yosys yosys=0.27_4_gb58664d44
+          conda create -y --prefix ./.conda-openroad openroad=2.0_7070_g0264023b6
+          conda create -y --prefix ./.conda-klayout klayout=0.28.5_98_g87e2def28
+          conda create -y --prefix ./.conda-signoff magic=8.3.376_0_g5e5879c netgen=1.5.250_0_g178b172
+
+          echo "# Tutorial configs" > tutorial.yml
+          echo "# pdk" > tutorial.yml
+          echo "technology.sky130.sky130A: $PWD/.conda-sky130/share/pdk/sky130A" >> tutorial.yml
+          echo "technology.sky130.sram22_sky130_macros: $PWD/sram22_sky130_macros" >> tutorial.yml
+          echo "" >> tutorial.yml
+          echo "# tools" >> tutorial.yml
+          echo "synthesis.yosys.yosys_bin: $PWD/.conda-yosys/bin/yosys" >> tutorial.yml
+          echo "par.openroad.openroad_bin: $PWD/.conda-openroad/bin/openroad" >> tutorial.yml
+          echo "par.openroad.klayout_bin: $PWD/.conda-klayout/bin/klayout" >> tutorial.yml
+          echo "drc.magic.magic_bin: $PWD/.conda-signoff/bin/magic" >> tutorial.yml
+          echo "lvs.netgen.netgen_bin: $PWD/.conda-signoff/bin/netgen" >> tutorial.yml
+          echo "" >> tutorial.yml
+          echo "# RocketTile clock name is 'clock'" >> tutorial.yml
+          echo "vlsi.inputs.clocks: [" >> tutorial.yml
+          echo "  {name: clock, period: 30ns, uncertainty: 3ns}" >> tutorial.yml
+          echo "]" >> tutorial.yml
+          echo "# speed up tutorial runs & declutter log output" >> tutorial.yml
+          echo "par.openroad.timing_driven: false" >> tutorial.yml
+          echo "par.openroad.write_reports: false" >> tutorial.yml
+
+          conda config --remove channels litex-hub
+          conda config --remove channels defaults
+
+          export tutorial=sky130-openroad
+          export EXTRA_CONFS="example-designs/sky130-openroad-rockettile.yml tutorial.yml"
+          export VLSI_TOP=RocketTile
+          make buildfile
+          make syn
+          # openroad freezes during some write commands after detailed route
+          # so need to stop the flow & run last step separately
+          make par HAMMER_EXTRA_ARGS="--stop_after_step extraction"
+          make redo-par HAMMER_EXTRA_ARGS="--start_before_step extraction"
+          make drc
+          # doesn't work for now bc of hammer sky130 plugin bug, fix in next release
+          # make lvs
+

  cleanup:
    name: cleanup
--- a/conda-reqs/chipyard.yaml
+++ b/conda-reqs/chipyard.yaml
@@ -1,5 +1,6 @@
 channels:
    - ucb-bar
+    - litex-hub
    - conda-forge
    - nodefaults

@@ -46,7 +47,6 @@ dependencies:
    - doit>=0.34.0
    - gitpython
    - humanfriendly
-    - e2fsprogs
    - ctags
    - bison
    - flex
@@ -102,7 +102,7 @@ dependencies:
    # hammer packages
    - sty
    - pip:
-        - hammer-vlsi[asap7]==1.0.1
+        - hammer-vlsi[asap7]==1.0.4

    # doc requirements
    - sphinx
@@ -135,6 +135,9 @@ dependencies:
    - pip:
        - sure
        - pylddwrap
+    
+    # hammer sky130 open-source vlsi flow
+    - open_pdks.sky130a

    # firesim ci shared packages
    - boto3
--- a/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
--- a/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
+++ b/conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
--- a/conda-reqs/esp-tools.yaml
+++ b/conda-reqs/esp-tools.yaml
@@ -1,5 +1,6 @@
 channels:
    - ucb-bar
+    - litex-hub
    - conda-forge
    - nodefaults

--- a/conda-reqs/riscv-tools.yaml
+++ b/conda-reqs/riscv-tools.yaml
@@ -1,5 +1,6 @@
 channels:
    - ucb-bar
+    - litex-hub
    - conda-forge
    - nodefaults

@@ -14,4 +15,4 @@ dependencies:
    # https://docs.conda.io/projects/conda/en/latest/user-guide/concepts/pkg-specs.html#package-match-specifications
    #   documentation on package_spec syntax for constraining versions

-    - riscv-tools=1.0.1 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
+    - riscv-tools=1.0.3 # from ucb-bar channel - https://github.com/ucb-bar/riscv-tools-feedstock
--- a/docs/Customization/Firrtl-Transforms.rst
+++ b/docs/Customization/Firrtl-Transforms.rst
@@ -10,15 +10,18 @@ Transforms are a powerful tool to take in the FIRRTL IR that is emitted from Chi

 The Scala FIRRTL Compiler and the MLIR FIRRTL Compiler
 ------------------------------------------------------
-In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler(SFC) and the MLIR FIRRTL compiler(MFC).
-They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster. In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
-compile CHIRRTL into Verilog(as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value, we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
+In Chipyard, two FIRRTL compilers work together to compile Chisel into Verilog. The Scala FIRRTL compiler (SFC) and the MLIR FIRRTL compiler (MFC).
+They are basically doing the same thing, except that MFC is written in C++ which makes compilation much faster (the generated Verilog will be different). In the default setting, the SFC will compile Chisel into CHIRRTL and MFC will
+compile CHIRRTL into Verilog (as of now, we are using SFC as a backup for cases when MFC doesn't work, e.g., when the design is using Fixed types). By setting the ``ENABLE_CUSTOM_FIRRTL_PASS`` env variable to a non-zero value,
+we can make the SFC compile Chisel into LowFIRRTL so that our custom FIRRTL passes are applied.
+
+For more information on MLIR FIRRTL Compiler, please visit https://mlir.llvm.org/ and https://circt.llvm.org/.

 Where to add transforms
 -----------------------

-In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Harness" file containing the test harness, which instantiates the DUT.
-The "Harness" file does not contain the DUT's module definition or any of its submodules.
+In Chipyard, the FIRRTL compiler is called multiple times to create a "Top" file that contains the DUT and a "Model" file containing the test harness, which instantiates the DUT.
+The "Model" file does not contain the DUT's module definition or any of its submodules.
 This is done by the ``tapeout`` SBT project (located in ``tools/barstools/tapeout``) which calls ``GenerateModelStageMain`` (a function that wraps the multiple FIRRTL compiler calls and extra transforms).

 .. literalinclude:: ../../common.mk
--- a/docs/Tools/FIRRTL.rst
+++ b/docs/Tools/FIRRTL.rst
@@ -3,8 +3,10 @@ FIRRTL

 `FIRRTL <https://github.com/freechipsproject/firrtl>`__ is an intermediate representation of your circuit.
 It is emitted by the Chisel compiler and is used to translate Chisel source files into another representation such as Verilog.
-Without going into too much detail, FIRRTL is consumed by a FIRRTL compiler (another Scala program) which passes the circuit through a series of circuit-level transformations.
+Without going into too much detail, FIRRTL is consumed by FIRRTL compilers which passes the circuit through a series of circuit-level transformations.
 An example of a FIRRTL pass (transformation) is one that optimizes out unused signals.
 Once the transformations are done, a Verilog file is emitted and the build process is done.

-For more information on please visit their `website <https://chisel-lang.org/firrtl/>`__.
+To see how FIRRTL is transformed to Verilog in Chipyard, please visit the :ref:`firrtl-transforms` section.
+
+For more information on FIRRTL, please visit their `website <https://chisel-lang.org/firrtl/>`__.
--- a/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
@@ -21,6 +21,12 @@ class FPGemminiRocketConfig extends Config(
  new chipyard.config.WithSystemBusWidth(128) ++
  new chipyard.config.AbstractConfig)

+class LeanGemminiRocketConfig extends Config(
+  new gemmini.LeanGemminiConfig ++                                 // use Lean Gemmini systolic array GEMM accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.WithSystemBusWidth(128) ++
+  new chipyard.config.AbstractConfig)
+
 class HwachaRocketConfig extends Config(
  new chipyard.config.WithHwachaTest ++
  new hwacha.DefaultHwachaConfig ++                              // use Hwacha vector accelerator
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -242,3 +242,14 @@ class WithDefaultFireSimBridges extends Config(
  new WithTracerVBridge ++
  new WithFireSimIOCellModels
 )
+
+// Shorthand to register all of the provided mmio-only bridges above
+class WithDefaultMMIOOnlyFireSimBridges extends Config(
+  new WithSerialBridge ++
+  new WithUARTBridge ++
+  new WithBlockDeviceBridge ++
+  new WithFASEDBridge ++
+  new WithFireSimMultiCycleRegfile ++
+  new WithFireSimFAME5 ++
+  new WithFireSimIOCellModels
+)
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -282,3 +282,15 @@ class FireSimNoMemPortConfig extends Config(
  new testchipip.WithBackingScratchpad ++
  new WithFireSimConfigTweaks ++
  new chipyard.RocketConfig)
+
+class FireSimRocketMMIOOnlyConfig extends Config(
+  new WithDefaultMMIOOnlyFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.RocketConfig)
+
+class FireSimGemminiRocketMMIOOnlyConfig extends Config(
+  new WithDefaultMMIOOnlyFireSimBridges ++
+  new WithDefaultMemModel ++
+  new WithFireSimConfigTweaks ++
+  new chipyard.LeanGemminiRocketConfig)
--- a/generators/gemmini
+++ b/generators/gemmini
--- a/generators/sha3
+++ b/generators/sha3
--- a/software/firemarshal
+++ b/software/firemarshal
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -46,9 +46,9 @@ VLSI_MODEL_DUT_NAME ?= chiptop
 # If overriding, this should be relative to $(vlsi_dir)
 VLSI_OBJ_DIR       ?= build
 ifneq ($(CUSTOM_VLOG),)
-	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/custom-$(VLSI_TOP)
+	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(VLSI_TOP)
 else
-	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(VLSI_TOP)
+	OBJ_DIR          ?= $(vlsi_dir)/$(VLSI_OBJ_DIR)/$(long_name)-$(TOP)
 endif

 #########################################################################################
@@ -118,6 +118,12 @@ endif

 $(SYN_CONF): $(VLSI_RTL)
 	mkdir -p $(dir $@)
+	echo "sim.inputs:" > $@
+	echo "  input_files:" >> $@
+	for x in $$(cat $(VLSI_RTL)); do \
+		echo '    - "'$$x'"' >> $@; \
+	done
+	echo "  input_files_meta: 'append'" >> $@
 	echo "synthesis.inputs:" >> $@
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  input_files:" >> $@
--- a/vlsi/example-designs/sky130-openroad-rockettile.yml
+++ b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -0,0 +1,60 @@
+# Override configurations in ../example-sky130.yml and example-designs
+
+# Specify clock signals
+# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+vlsi.inputs.clocks: [
+  {name: "clock", period: "30ns", uncertainty: "3ns"}
+]
+
+# Placement Constraints
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "RocketTile"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 3000
+    margins:
+      left: 10
+      right: 0
+      top: 10
+      bottom: 10
+
+  # Place SRAM memory instances
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 450
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 850
+    orientation: r90
+  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "RocketTile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90
--- a/vlsi/example-designs/sky130-openroad.yml
+++ b/vlsi/example-designs/sky130-openroad.yml
@@ -37,3 +37,56 @@ par.openroad:
 # DRC/LVS configuration
 drc.magic.generate_only: true
 lvs.netgen.generate_only: true
+
+
+# Placement Constraints
+vlsi.inputs.placement_constraints:
+  - path: "ChipTop"
+    type: toplevel
+    x: 0
+    y: 0
+    width: 4000
+    height: 3000
+    margins:
+      left: 10
+      right: 0
+      top: 10
+      bottom: 10
+
+  # Place SRAM memory instances
+  # SRAM paths and configurations are slightly different due to ENABLE_YOSYS_FLOW flag
+  # data cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 50
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 450
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 850
+    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1250
+    orientation: r90
+ 
+  # tag array
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 1600
+    orientation: r90
+
+  # instruction cache
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+    type: hardmacro
+    x: 50
+    y: 2100
+    orientation: r90
--- a/vlsi/example-sky130.yml
+++ b/vlsi/example-sky130.yml
@@ -43,27 +43,12 @@ vlsi.inputs.placement_constraints:

  # Place SRAM memory instances
    # data cache
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 50
    orientation: r90
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 450
-    orientation: r90
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 850
-    orientation: r90
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 1250
-    orientation: r90
- 
+
  # tag array
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
    type: hardmacro
@@ -72,7 +57,7 @@ vlsi.inputs.placement_constraints:
    orientation: r90

  # instruction cache
-  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
    type: hardmacro
    x: 50
    y: 2100
--- a/vlsi/hammer-cadence-plugins
+++ b/vlsi/hammer-cadence-plugins
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -10,7 +10,7 @@ $(SIM_CONF): $(sim_common_files)
 	echo "  top_module: $(VLSI_TOP)" >> $@
 	echo "  tb_name: ''" >> $@  # don't specify -top
 	echo "  input_files:" >> $@
-	for x in $$(cat $(sim_common_files)); do \
+	for x in $$(comm -23 <(cat $(MODEL_MODS_FILELIST) $(MODEL_BB_MODS_FILELIST) | sort -u) <(sort $(VLSI_RTL))) $(MODEL_SMEMS_FILE) $(SIM_FILE_REQS); do \
 		echo '    - "'$$x'"' >> $@; \
 	done
 	echo "  input_files_meta: 'append'" >> $@
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -30,7 +30,10 @@ ifeq ($(tutorial),sky130-openroad)
    TOOLS_CONF        ?= example-openroad.yml
    TECH_CONF         ?= example-sky130.yml
    DESIGN_CONF       ?= example-designs/sky130-openroad.yml
-    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), example-designs/sky130-rocket.yml, )
+    EXTRA_CONFS       ?= $(if $(filter $(VLSI_TOP),Rocket), \
+                            example-designs/sky130-rocket.yml, \
+                            $(if $(filter $(VLSI_TOP),RocketTile), \
+                                example-designs/sky130-openroad-rockettile.yml, ))
    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONF) $(EXTRA_CONFS)
    VLSI_OBJ_DIR      ?= build-sky130-openroad
    # Yosys compatibility for CIRCT-generated Verilog, at the expense of elaboration time.