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Fix for modern CY

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This commit is contained in:
abejgonzalez
2023-07-12 16:24:04 -07:00
parent 6f8041bf82
commit 783084f0ca
5 changed files with 18 additions and 17 deletions
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2
generators/chipyard/src/main/scala/harness/TestHarness.scala
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@@ -34,5 +34,5 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessInst
def referenceClock = clock def referenceClock = clock
def referenceReset = reset def referenceReset = reset
instantiateChipTops() val lazyDuts = instantiateChipTops()
} }

10
generators/chipyard/src/main/scala/upf/ChipTopUPF.scala
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@@ -1,12 +1,12 @@
// See LICENSE for license details // See LICENSE for license details
package chipyard.upf package chipyard.upf
import scala.collection.mutable.ListBuffer import scala.collection.mutable.{ListBuffer}
import scalax.collection.mutable.Graph import scalax.collection.mutable.{Graph}
import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._ import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._
import chipyard.TestHarness import chipyard.harness.{TestHarness}
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.{LazyModule}
object ChipTopUPF { object ChipTopUPF {
@@ -87,4 +87,4 @@ object ChipTopUPF {
} }
case object ChipTopUPFAspect extends UPFAspect[chipyard.TestHarness](ChipTopUPF.default) case object ChipTopUPFAspect extends UPFAspect[chipyard.harness.TestHarness](ChipTopUPF.default)

11
generators/chipyard/src/main/scala/upf/UPFAspect.scala
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@@ -1,17 +1,18 @@
// See LICENSE for license details // See LICENSE for license details
package chipyard.upf package chipyard.upf
import chisel3.aop.Aspect import chisel3.aop.{Aspect}
import firrtl.{AnnotationSeq} import firrtl.{AnnotationSeq}
import chipyard.TestHarness import chipyard.harness.{TestHarness}
import freechips.rocketchip.stage.phases.TargetDirKey import freechips.rocketchip.stage.phases.{TargetDirKey}
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.{LazyModule}
abstract class UPFAspect[T <: TestHarness](upf: UPFFunc.UPFFunction) extends Aspect[T] { abstract class UPFAspect[T <: TestHarness](upf: UPFFunc.UPFFunction) extends Aspect[T] {
final override def toAnnotation(top: T): AnnotationSeq = { final override def toAnnotation(top: T): AnnotationSeq = {
UPFFunc.UPFPath = top.p(TargetDirKey) + "/upf" UPFFunc.UPFPath = top.p(TargetDirKey) + "/upf"
upf(top.lazyDut) require(top.lazyDuts.length == 1) // currently only supports 1 chiptop
upf(top.lazyDuts.head)
AnnotationSeq(Seq()) // noop AnnotationSeq(Seq()) // noop
} }

8
generators/chipyard/src/main/scala/upf/UPFGen.scala
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@@ -1,13 +1,13 @@
// See LICENSE for license details // See LICENSE for license details
package chipyard.upf package chipyard.upf
import java.io.FileWriter import java.io.{FileWriter}
import java.nio.file.{Paths, Files} import java.nio.file.{Paths, Files}
import scala.collection.mutable.ListBuffer import scala.collection.mutable.{ListBuffer}
import scalax.collection.mutable.Graph import scalax.collection.mutable.{Graph}
import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._ import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.{LazyModule}
case class PowerDomain (val name: String, val modules: ListBuffer[LazyModule], case class PowerDomain (val name: String, val modules: ListBuffer[LazyModule],
val isTop: Boolean, val isGated: Boolean, val isTop: Boolean, val isGated: Boolean,

4
generators/chipyard/src/main/scala/upf/UPFInputs.scala
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@@ -13,10 +13,10 @@ object UPFInputs {
PowerDomainInput(name="PD_top", isTop=true, moduleList=List("DigitalTop"), PowerDomainInput(name="PD_top", isTop=true, moduleList=List("DigitalTop"),
parentPD="", childrenPDs=List("PD_RocketTile1", "PD_RocketTile2"), parentPD="", childrenPDs=List("PD_RocketTile1", "PD_RocketTile2"),
isGated=false, highVoltage=3.9, lowVoltage=3.4), isGated=false, highVoltage=3.9, lowVoltage=3.4),
PowerDomainInput(name="PD_RocketTile1", isTop=false, moduleList=List("RocketTile"), PowerDomainInput(name="PD_RocketTile1", isTop=false, moduleList=List("tile_prci_domain"),
parentPD="PD_top", childrenPDs=List(), parentPD="PD_top", childrenPDs=List(),
isGated=false, highVoltage=3.9, lowVoltage=3.1), isGated=false, highVoltage=3.9, lowVoltage=3.1),
PowerDomainInput(name="PD_RocketTile2", isTop=false, moduleList=List("RocketTile_1"), PowerDomainInput(name="PD_RocketTile2", isTop=false, moduleList=List("tile_prci_domain_1"),
parentPD="PD_top", childrenPDs=List(), parentPD="PD_top", childrenPDs=List(),
isGated=false, highVoltage=3.9, lowVoltage=3.2), isGated=false, highVoltage=3.9, lowVoltage=3.2),
) )