From 783084f0ca82f248194fc8a229d313db72ee9dbf Mon Sep 17 00:00:00 2001
From: abejgonzalez <abe.j.gonza@gmail.com>
Date: Wed, 12 Jul 2023 16:24:04 -0700
Subject: [PATCH] Fix for modern CY

---
 .../chipyard/src/main/scala/harness/TestHarness.scala |  2 +-
 .../chipyard/src/main/scala/upf/ChipTopUPF.scala      | 10 +++++-----
 .../chipyard/src/main/scala/upf/UPFAspect.scala       | 11 ++++++-----
 generators/chipyard/src/main/scala/upf/UPFGen.scala   |  8 ++++----
 .../chipyard/src/main/scala/upf/UPFInputs.scala       |  4 ++--
 5 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/generators/chipyard/src/main/scala/harness/TestHarness.scala b/generators/chipyard/src/main/scala/harness/TestHarness.scala
index e1f659b4..459c6511 100644
--- a/generators/chipyard/src/main/scala/harness/TestHarness.scala
+++ b/generators/chipyard/src/main/scala/harness/TestHarness.scala
@@ -34,5 +34,5 @@ class TestHarness(implicit val p: Parameters) extends Module with HasHarnessInst
   def referenceClock = clock
   def referenceReset = reset
 
-  instantiateChipTops()
+  val lazyDuts = instantiateChipTops()
 }
diff --git a/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala b/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala
index 9356d591..acbdb790 100644
--- a/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala
+++ b/generators/chipyard/src/main/scala/upf/ChipTopUPF.scala
@@ -1,12 +1,12 @@
 // See LICENSE for license details
 package chipyard.upf
 
-import scala.collection.mutable.ListBuffer
-import scalax.collection.mutable.Graph
+import scala.collection.mutable.{ListBuffer}
+import scalax.collection.mutable.{Graph}
 import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._
 
-import chipyard.TestHarness
-import freechips.rocketchip.diplomacy.LazyModule
+import chipyard.harness.{TestHarness}
+import freechips.rocketchip.diplomacy.{LazyModule}
 
 object ChipTopUPF {
 
@@ -87,4 +87,4 @@ object ChipTopUPF {
 
 }
 
-case object ChipTopUPFAspect extends UPFAspect[chipyard.TestHarness](ChipTopUPF.default)
+case object ChipTopUPFAspect extends UPFAspect[chipyard.harness.TestHarness](ChipTopUPF.default)
diff --git a/generators/chipyard/src/main/scala/upf/UPFAspect.scala b/generators/chipyard/src/main/scala/upf/UPFAspect.scala
index e09ad910..65508684 100644
--- a/generators/chipyard/src/main/scala/upf/UPFAspect.scala
+++ b/generators/chipyard/src/main/scala/upf/UPFAspect.scala
@@ -1,17 +1,18 @@
 // See LICENSE for license details
 package chipyard.upf
 
-import chisel3.aop.Aspect
+import chisel3.aop.{Aspect}
 import firrtl.{AnnotationSeq}
-import chipyard.TestHarness
-import freechips.rocketchip.stage.phases.TargetDirKey
-import freechips.rocketchip.diplomacy.LazyModule
+import chipyard.harness.{TestHarness}
+import freechips.rocketchip.stage.phases.{TargetDirKey}
+import freechips.rocketchip.diplomacy.{LazyModule}
 
 abstract class UPFAspect[T <: TestHarness](upf: UPFFunc.UPFFunction) extends Aspect[T] {
 
   final override def toAnnotation(top: T): AnnotationSeq = {
     UPFFunc.UPFPath = top.p(TargetDirKey) + "/upf"
-    upf(top.lazyDut)
+    require(top.lazyDuts.length == 1) // currently only supports 1 chiptop
+    upf(top.lazyDuts.head)
     AnnotationSeq(Seq()) // noop
   }
 
diff --git a/generators/chipyard/src/main/scala/upf/UPFGen.scala b/generators/chipyard/src/main/scala/upf/UPFGen.scala
index 47475727..559be1e3 100644
--- a/generators/chipyard/src/main/scala/upf/UPFGen.scala
+++ b/generators/chipyard/src/main/scala/upf/UPFGen.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details
 package chipyard.upf
 
-import java.io.FileWriter
+import java.io.{FileWriter}
 import java.nio.file.{Paths, Files}
-import scala.collection.mutable.ListBuffer
-import scalax.collection.mutable.Graph
+import scala.collection.mutable.{ListBuffer}
+import scalax.collection.mutable.{Graph}
 import scalax.collection.GraphPredef._, scalax.collection.GraphEdge._
 
-import freechips.rocketchip.diplomacy.LazyModule
+import freechips.rocketchip.diplomacy.{LazyModule}
 
 case class PowerDomain (val name: String, val modules: ListBuffer[LazyModule],
                         val isTop: Boolean, val isGated: Boolean,
diff --git a/generators/chipyard/src/main/scala/upf/UPFInputs.scala b/generators/chipyard/src/main/scala/upf/UPFInputs.scala
index 438b7e7b..fbbc4452 100644
--- a/generators/chipyard/src/main/scala/upf/UPFInputs.scala
+++ b/generators/chipyard/src/main/scala/upf/UPFInputs.scala
@@ -13,10 +13,10 @@ object UPFInputs {
         PowerDomainInput(name="PD_top", isTop=true, moduleList=List("DigitalTop"),
                          parentPD="", childrenPDs=List("PD_RocketTile1", "PD_RocketTile2"),
                          isGated=false, highVoltage=3.9, lowVoltage=3.4),
-        PowerDomainInput(name="PD_RocketTile1", isTop=false, moduleList=List("RocketTile"),
+        PowerDomainInput(name="PD_RocketTile1", isTop=false, moduleList=List("tile_prci_domain"),
                          parentPD="PD_top", childrenPDs=List(),
                          isGated=false, highVoltage=3.9, lowVoltage=3.1),
-        PowerDomainInput(name="PD_RocketTile2", isTop=false, moduleList=List("RocketTile_1"),
+        PowerDomainInput(name="PD_RocketTile2", isTop=false, moduleList=List("tile_prci_domain_1"),
                          parentPD="PD_top", childrenPDs=List(),
                          isGated=false, highVoltage=3.9, lowVoltage=3.2),
     )