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Change macrocompiler to support FIRRTL 1.3 -- not backwards compatible

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This commit is contained in:
Albert Magyar
2020-05-06 21:40:47 +00:00
parent acda0a3490
commit 757c39ac1c
2 changed files with 22 additions and 30 deletions
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8
macros/src/main/scala/Utils.scala
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@@ -6,12 +6,16 @@ import firrtl._
import firrtl.ir._
import firrtl.PrimOps
import firrtl.passes.memlib.{MemConf, MemPort, ReadPort, WritePort, ReadWritePort, MaskedWritePort, MaskedReadWritePort}
import firrtl.Utils.{ceilLog2, BoolType}
import firrtl.Utils.BoolType
import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge, MacroExtraPort}
import java.io.File
import scala.language.implicitConversions
object MacroCompilerMath {
def ceilLog2(x: BigInt): Int = (x-1).bitLength
}
class FirrtlMacroPort(port: MacroPort) {
val src = port
@@ -19,7 +23,7 @@ class FirrtlMacroPort(port: MacroPort) {
val isWriter = port.input.nonEmpty && port.output.isEmpty
val isReadWriter = port.input.nonEmpty && port.output.nonEmpty
val addrType = UIntType(IntWidth(ceilLog2(port.depth.get) max 1))
val addrType = UIntType(IntWidth(MacroCompilerMath.ceilLog2(port.depth.get) max 1))
val dataType = UIntType(IntWidth(port.width.get))
val maskType = UIntType(IntWidth(port.width.get / port.effectiveMaskGran))