From 757c39ac1cd5bc79fad948a703ea23f5748e2d93 Mon Sep 17 00:00:00 2001
From: Albert Magyar <albert.magyar@gmail.com>
Date: Wed, 6 May 2020 21:40:47 +0000
Subject: [PATCH] Change macrocompiler to support FIRRTL 1.3 -- not backwards
 compatible

---
 macros/src/main/scala/MacroCompiler.scala | 44 +++++++++--------------
 macros/src/main/scala/Utils.scala         |  8 +++--
 2 files changed, 22 insertions(+), 30 deletions(-)

diff --git a/macros/src/main/scala/MacroCompiler.scala b/macros/src/main/scala/MacroCompiler.scala
index 652e36e9..5d1be9c7 100644
--- a/macros/src/main/scala/MacroCompiler.scala
+++ b/macros/src/main/scala/MacroCompiler.scala
@@ -289,8 +289,8 @@ class MacroCompilerPass(mems: Option[Seq[Macro]],
      * address bits into account. */
     if (mem.src.depth > lib.src.depth) {
       mem.src.ports foreach { port =>
-        val high = ceilLog2(mem.src.depth)
-        val low = ceilLog2(lib.src.depth)
+        val high = MacroCompilerMath.ceilLog2(mem.src.depth)
+        val low = MacroCompilerMath.ceilLog2(lib.src.depth)
         val ref = WRef(port.address.name)
         val nodeName = s"${ref.name}_sel"
         val tpe = UIntType(IntWidth(high-low))
@@ -738,7 +738,7 @@ class MacroCompiler extends Compiler {
 
   def transforms: Seq[Transform] =
     Seq(new MacroCompilerTransform) ++
-      getLoweringTransforms(firrtl.HighForm, firrtl.LowForm) ++
+      getLoweringTransforms(firrtl.ChirrtlForm, firrtl.LowForm) ++
       Seq(new MacroCompilerOptimizations)
 }
 
@@ -834,36 +834,24 @@ object MacroCompiler extends App {
             )
           ))
         )
-        // Append a NoDCEAnnotation to avoid dead code elimination removing the non-parent SRAMs
-        val state = CircuitState(circuit, HighForm, annotations :+ NoDCEAnnotation)
 
-        // Run the compiler.
-        val result = new MacroCompiler().compileAndEmit(state)
+        // The actual MacroCompilerTransform basically just generates an input circuit
+        val macroCompilerInput = CircuitState(circuit, HighForm, annotations)
+        val macroCompiled = (new MacroCompilerTransform).execute(macroCompilerInput)
 
-        // Write output FIRRTL file.
-        params.get(Firrtl) match {
-          case Some(firrtlFile: String) => {
-            val fileWriter = new FileWriter(new File(firrtlFile))
-            fileWriter.write(result.circuit.serialize)
-            fileWriter.close()
-          }
-          case None =>
+
+        // Since the MacroCompiler defines its own CLI, reconcile this with FIRRTL options
+        val firOptions = new ExecutionOptionsManager("macrocompiler") with HasFirrtlOptions {
+          firrtlOptions = FirrtlExecutionOptions(
+            outputFileNameOverride = params.get(Verilog).getOrElse(""),
+            noDCE = true,
+            firrtlSource = Some(macroCompiled.circuit.serialize)
+          )
         }
 
-        // Write output Verilog file.
-        params.get(Verilog) match {
-          case Some(verilogFile: String) => {
-            // Open the writer for the output Verilog file.
-            val verilogWriter = new FileWriter(new File(verilogFile))
+        // Run FIRRTL compiler
+        Driver.execute(firOptions)
 
-            // Extract Verilog circuit and write it.
-            verilogWriter.write(result.getEmittedCircuit.value)
-
-            // Close the writer.
-            verilogWriter.close()
-          }
-          case None =>
-        }
         params.get(HammerIR) match {
           case Some(hammerIRFile: String) => {
             val lines = Source.fromFile(hammerIRFile).getLines().toList
diff --git a/macros/src/main/scala/Utils.scala b/macros/src/main/scala/Utils.scala
index ba8c664d..c416ca6a 100644
--- a/macros/src/main/scala/Utils.scala
+++ b/macros/src/main/scala/Utils.scala
@@ -6,12 +6,16 @@ import firrtl._
 import firrtl.ir._
 import firrtl.PrimOps
 import firrtl.passes.memlib.{MemConf, MemPort, ReadPort, WritePort, ReadWritePort, MaskedWritePort, MaskedReadWritePort}
-import firrtl.Utils.{ceilLog2, BoolType}
+import firrtl.Utils.BoolType
 import mdf.macrolib.{Constant, MacroPort, SRAMMacro}
 import mdf.macrolib.{PolarizedPort, PortPolarity, ActiveLow, ActiveHigh, NegativeEdge, PositiveEdge, MacroExtraPort}
 import java.io.File
 import scala.language.implicitConversions
 
+object MacroCompilerMath {
+  def ceilLog2(x: BigInt): Int = (x-1).bitLength
+}
+
 class FirrtlMacroPort(port: MacroPort) {
   val src = port
 
@@ -19,7 +23,7 @@ class FirrtlMacroPort(port: MacroPort) {
   val isWriter = port.input.nonEmpty && port.output.isEmpty
   val isReadWriter = port.input.nonEmpty && port.output.nonEmpty
 
-  val addrType = UIntType(IntWidth(ceilLog2(port.depth.get) max 1))
+  val addrType = UIntType(IntWidth(MacroCompilerMath.ceilLog2(port.depth.get) max 1))
   val dataType = UIntType(IntWidth(port.width.get))
   val maskType = UIntType(IntWidth(port.width.get / port.effectiveMaskGran))