Convert fire() to fire
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@@ -52,7 +52,7 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
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state := s_resp
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}
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when (mem.d.fire()) {
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when (mem.d.fire) {
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state := Mux(bytesLeft === 0.U, s_done, s_write)
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}
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}
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@@ -115,7 +115,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
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// When a new transaction is ready on the input, we will have new data to output
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// next cycle. Take this data in
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when (io.in.fire()) {
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when (io.in.fire) {
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hasNewData := 1.U
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inputReg := io.in.bits.data
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}
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@@ -123,7 +123,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
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// We should output data when our cell has new data to output and is ready to
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// recieve new data. This insures that every cell in the chain passes its data
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// on at the same time
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io.out.valid := hasNewData & io.in.fire()
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io.out.valid := hasNewData & io.in.fire
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io.out.bits.data := inputReg
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// Compute carry
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