diff --git a/generators/boom b/generators/boom
index 68e76740..42dc388e 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 68e767400cc5b0ea46ae797d88f0908729de8fce
+Subproject commit 42dc388e755b8a1b7631e355d532d9b6b6730743
diff --git a/generators/chipyard/src/main/scala/example/InitZero.scala b/generators/chipyard/src/main/scala/example/InitZero.scala
index c351a4dd..a9885d34 100644
--- a/generators/chipyard/src/main/scala/example/InitZero.scala
+++ b/generators/chipyard/src/main/scala/example/InitZero.scala
@@ -52,7 +52,7 @@ class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
     state := s_resp
   }
 
-  when (mem.d.fire()) {
+  when (mem.d.fire) {
     state := Mux(bytesLeft === 0.U, s_done, s_write)
   }
 }
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index b92ca181..f45b318c 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -115,7 +115,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
 
   // When a new transaction is ready on the input, we will have new data to output
   // next cycle. Take this data in
-  when (io.in.fire()) {
+  when (io.in.fire) {
     hasNewData := 1.U
     inputReg := io.in.bits.data
   }
@@ -123,7 +123,7 @@ class GenericFIRDirectCell[T<:Data:Ring](genIn: T, genOut: T) extends Module {
   // We should output data when our cell has new data to output and is ready to
   // recieve new data. This insures that every cell in the chain passes its data
   // on at the same time
-  io.out.valid := hasNewData & io.in.fire()
+  io.out.valid := hasNewData & io.in.fire
   io.out.bits.data := inputReg
 
   // Compute carry
diff --git a/generators/gemmini b/generators/gemmini
index 5687ff9f..a99a4eee 160000
--- a/generators/gemmini
+++ b/generators/gemmini
@@ -1 +1 @@
-Subproject commit 5687ff9f809cb3eb0acafc1ac2f73a57d0a67b2c
+Subproject commit a99a4eee1e6c101eed392e22b271f24f65744629
diff --git a/generators/hwacha b/generators/hwacha
index 062e46e3..34aaffd2 160000
--- a/generators/hwacha
+++ b/generators/hwacha
@@ -1 +1 @@
-Subproject commit 062e46e36d1e5fbe486ab2db54bda62f71fd3dab
+Subproject commit 34aaffd206a3fe07f6bea05588a20862bf95a68b
diff --git a/generators/icenet b/generators/icenet
index 2d4022de..af7253de 160000
--- a/generators/icenet
+++ b/generators/icenet
@@ -1 +1 @@
-Subproject commit 2d4022de45bae66eef1817ac9ef18708961ec6ea
+Subproject commit af7253dea91c48b13f43f2da5ee2abae170aaa36
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index 7b19a1c7..f8892559 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit 7b19a1c74fa36217db288987ac8d63e699eda1b4
+Subproject commit f8892559c6b499d2b80a3bc095fac99b15ea8a6a
diff --git a/generators/testchipip b/generators/testchipip
index c8f4cf2f..aaf0cd18 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit c8f4cf2fb522fe48fbf4f35df0d62d1cdb1a12cd
+Subproject commit aaf0cd18100a1b6b11f554b9acfcf2c01c0d40a4
diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala
index 712cffc1..2e0084ec 100644
--- a/generators/tracegen/src/main/scala/Tile.scala
+++ b/generators/tracegen/src/main/scala/Tile.scala
@@ -66,10 +66,10 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
   tracegen_uop.ctrl.is_sta  := isWrite(io.tracegen.req.bits.cmd)
   tracegen_uop.ctrl.is_std  := isWrite(io.tracegen.req.bits.cmd)
 
-  io.lsu.dis_uops(0).valid         := io.tracegen.req.fire()
+  io.lsu.dis_uops(0).valid         := io.tracegen.req.fire
   io.lsu.dis_uops(0).bits          := tracegen_uop
 
-  when (io.tracegen.req.fire()) {
+  when (io.tracegen.req.fire) {
     rob_tail := WrapInc(rob_tail, rob_sz)
     rob_bsy(rob_tail)   := true.B
     rob_uop(rob_tail)   := tracegen_uop
@@ -111,7 +111,7 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
 
   assert(!io.lsu.lxcpt.valid)
 
-  io.lsu.exe(0).req.valid     := RegNext(io.tracegen.req.fire())
+  io.lsu.exe(0).req.valid     := RegNext(io.tracegen.req.fire)
   io.lsu.exe(0).req.bits      := DontCare
   io.lsu.exe(0).req.bits.uop  := RegNext(tracegen_uop)
   io.lsu.exe(0).req.bits.addr := RegNext(io.tracegen.req.bits.addr)