Fix RationalRockettiles not getting picked up in MulticlockRocketConfig
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@@ -86,6 +86,7 @@ class MbusScratchpadRocketConfig extends Config(
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// DOC include end: mbusscratchpadrocket
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// DOC include end: mbusscratchpadrocket
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class MulticlockRocketConfig extends Config(
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class MulticlockRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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// Frequency specifications
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// Frequency specifications
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new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540
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new chipyard.config.WithTileFrequency(1600.0) ++ // Matches the maximum frequency of U540
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@@ -96,7 +97,6 @@ class MulticlockRocketConfig extends Config(
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// Crossing specifications
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// Crossing specifications
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new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
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new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossing between PBUS and CBUS
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new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
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new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++ // Add Async crossings between backside of L2 and MBUS
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new freechips.rocketchip.subsystem.WithRationalRocketTiles ++ // Add rational crossings between RocketTile and uncore
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new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
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new testchipip.WithAsynchronousSerialSlaveCrossing ++ // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
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new chipyard.config.AbstractConfig)
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new chipyard.config.AbstractConfig)
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