Merge branch 'main' into klayout-docs

2023-07-10 09:21:18 -07:00
parent 5f54876de2 687e791b80
commit 6f90102770
43 changed files with 628 additions and 195 deletions
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -91,11 +91,6 @@ dir="tools"
 branches=("master" "dev")
 search

-submodules=("firesim")
-dir="sims"
-branches=("master" "main" "dev" "1.13.x")
-search
-
 submodules=("fpga-shells")
 dir="fpga"
 branches=("main")
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -29,7 +29,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
 # key value store to get the build groups
 declare -A grouping
 grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
-grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike"
+grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered"
 grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla"
 grouping["group-constellation"]="chipyard-constellation"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -56,7 +56,8 @@ mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
 mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
 mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
 mapping["chipyard-manyperipherals"]=" CONFIG=ManyPeripheralsRocketConfig EXTRA_SIM_FLAGS='+spiflash0=${LOCAL_CHIPYARD_DIR}/tests/spiflash.img'"
-mapping["chipyard-chiplike"]=" CONFIG=ChipLikeQuadRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
+mapping["chipyard-chiplike"]=" CONFIG=ChipLikeRocketConfig MODEL=FlatTestHarness MODEL_PACKAGE=chipyard.example verilog"
+mapping["chipyard-tethered"]=" CONFIG=VerilatorCITetheredChipLikeRocketConfig"
 mapping["chipyard-cloneboom"]=" CONFIG=Cloned64MegaBoomConfig verilog"
 mapping["chipyard-nocores"]=" CONFIG=NoCoresConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
--- a/.github/scripts/install-conda.sh
+++ b/.github/scripts/install-conda.sh
@@ -3,7 +3,7 @@
 export HOME="${HOME:-/root}"

 CONDA_INSTALL_PREFIX=/opt/conda
-CONDA_INSTALLER_VERSION=22.11.1-4
+CONDA_INSTALLER_VERSION=23.1.0-1
 CONDA_INSTALLER="https://github.com/conda-forge/miniforge/releases/download/${CONDA_INSTALLER_VERSION}/Miniforge3-${CONDA_INSTALLER_VERSION}-Linux-x86_64.sh"
 CONDA_CMD="conda" # some installers install mamba or micromamba

--- a/.github/scripts/run-tests.sh
+++ b/.github/scripts/run-tests.sh
@@ -10,13 +10,14 @@ SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
 source $SCRIPT_DIR/defaults.sh

 DISABLE_SIM_PREREQ="BREAK_SIM_PREREQ=1"
+MAPPING_FLAGS=${mapping[$1]}

 run_bmark () {
-    make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $@
+    make run-bmark-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }

 run_asm () {
-    make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $@
+    make run-asm-tests-fast -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }

 run_both () {
@@ -25,135 +26,137 @@ run_both () {
 }

 run_tracegen () {
-    make tracegen -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $@
+    make tracegen -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }

-run_none () {
-    make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ run-binary-fast BINARY=none $@
+run_binary () {
+    make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS $@
 }

 case $1 in
    chipyard-rocket)
-        run_bmark ${mapping[$1]}
+        run_bmark
        make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADMEM=1 BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv
+        # Test run-binary with and without loadmem
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv
        ;;
    chipyard-dmirocket)
+        # Test checkpoint-restore
        $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
+        run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
        ;;
    chipyard-boom)
-        run_bmark ${mapping[$1]}
+        run_bmark
        ;;
    chipyard-shuttle)
        run_bmark ${mapping[$1]}
        ;;
    chipyard-dmiboom)
+        # Test checkpoint-restore
        $LOCAL_CHIPYARD_DIR/scripts/generate-ckpt.sh -b $RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -i 10000
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
+        run_binary LOADARCH=$PWD/dhrystone.riscv.0x80000000.10000.loadarch
        ;;
    chipyard-spike)
-        run_bmark ${mapping[$1]}
+        run_bmark
        ;;
    chipyard-hetero)
-        run_bmark ${mapping[$1]}
+        run_bmark
        ;;
    chipyard-prefetchers)
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
        ;;
    rocketchip)
-        run_bmark ${mapping[$1]}
+        run_bmark
        ;;
    chipyard-hwacha)
-        make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
+        make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS
        ;;
    chipyard-gemmini)
        GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
        rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
        cd $LOCAL_SIM_DIR
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
+        run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/aligned-baremetal
+        run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal
+        run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
        ;;
    chipyard-sha3)
        (cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv
        ;;
    chipyard-mempress)
        (cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
        ;;
    chipyard-manymmioaccels)
 	make -C $LOCAL_CHIPYARD_DIR/tests

 	# test streaming-passthrough
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-passthrough.riscv

 	# test streaming-fir
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} run-binary-fast BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/streaming-fir.riscv

 	# test fft
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv
 	;;
    chipyard-nvdla)
 	make -C $LOCAL_CHIPYARD_DIR/tests
-
-	# test nvdla
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary-fast
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv
 	;;
    chipyard-manyperipherals)
-	# SPI Flash read tests, then bmark tests
-
+	# SPI Flash read tests
        make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv run-binary-fast
-
-	run_bmark ${mapping[$1]}
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashread.riscv
        ;;
    chipyard-spiflashwrite)
        make -C $LOCAL_CHIPYARD_DIR/tests
-        make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv run-binary-fast
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/spiflashwrite.riscv
        [[ "`xxd $LOCAL_CHIPYARD_DIR/tests/spiflash.img  | grep 1337\ 00ff\ aa55\ face | wc -l`" == "6" ]] || false
        ;;
+    chipyard-tethered)
+        make -C $LOCAL_CHIPYARD_DIR/tests
+        run_binary BINARY=$LOCAL_CHIPYARD_DIR/tests/hello.riscv LOADMEM=1 EXTRA_SIM_FLAGS="+cflush_addr=0x2010200"
+        ;;
    tracegen)
-        run_tracegen ${mapping[$1]}
+        run_tracegen
        ;;
    tracegen-boom)
-        run_tracegen ${mapping[$1]}
+        run_tracegen
        ;;
    chipyard-cva6)
-        make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
+        run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
        ;;
    chipyard-ibex)
        # Ibex cannot run the riscv-tests binaries for some reason
-        # make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple
+        # run_binary BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/isa/rv32ui-p-simple
        ;;
    chipyard-sodor)
-        run_asm ${mapping[$1]}
+        run_asm
        ;;
    chipyard-constellation)
-        make run-binary-hex BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
+        run_binary LOADMEM=1 BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv
        ;;
    icenet)
-        run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    testchipip)
-        run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    constellation)
-        run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    rocketchip-amba)
-        run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    rocketchip-tlsimple)
-	run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    rocketchip-tlwidth)
-	run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    rocketchip-tlxbar)
-	run_none ${mapping[$1]}
+        run_binary BINARY=none
        ;;
    *)
        echo "No set of tests for $1. Did you spell it right?"
--- a/.github/workflows/chipyard-full-flow.yml
+++ b/.github/workflows/chipyard-full-flow.yml
@@ -6,6 +6,9 @@ on:
    branches:
      - main
      - '1.[0-9]*.x'
+  schedule:
+    # run at 00:00 on sunday
+    - cron: "0 0 * * 0"

 defaults:
  run:
--- a/.github/workflows/chipyard-run-tests.yml
+++ b/.github/workflows/chipyard-run-tests.yml
@@ -718,6 +718,29 @@ jobs:
          group-key: "group-peripherals"
          project-key: "chipyard-manyperipherals"

+  chipyard-tethered-run-tests:
+    name: chipyard-tethered-run-tests
+    needs: prepare-chipyard-peripherals
+    runs-on: self-hosted
+    steps:
+      - name: Delete old checkout
+        run: |
+            ls -alh .
+            rm -rf ${{ github.workspace }}/* || true
+            rm -rf ${{ github.workspace }}/.* || true
+            ls -alh .
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Git workaround
+        uses: ./.github/actions/git-workaround
+      - name: Create conda env
+        uses: ./.github/actions/create-conda-env
+      - name: Run tests
+        uses: ./.github/actions/run-tests
+        with:
+          group-key: "group-peripherals"
+          project-key: "chipyard-tethered"
+
  chipyard-sha3-run-tests:
    name: chipyard-sha3-run-tests
    needs: prepare-chipyard-accels
@@ -1080,6 +1103,7 @@ jobs:
            chipyard-dmirocket-run-tests,
            chipyard-spiflashwrite-run-tests,
            chipyard-manyperipherals-run-tests,
+            chipyard-tethered-run-tests,
            chipyard-sha3-run-tests,
            chipyard-gemmini-run-tests,
            chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
--- a/.github/workflows/config/release-notes.json
+++ b/.github/workflows/config/release-notes.json
@@ -0,0 +1,56 @@
+{
+    "categories": [
+      {
+        "title": "## Added",
+        "labels": ["changelog:added"]
+      },
+      {
+        "title": "## Changed",
+        "labels": ["changelog:changed"]
+      },
+      {
+        "title": "## Fixed",
+        "labels": ["changelog:fixed"]
+      },
+      {
+        "title": "## Removed",
+        "labels": ["changelog:removed"]
+      },
+      {
+        "title": "## Uncategorized",
+        "labels": []
+      }
+    ],
+    "ignore_labels": [
+      "changelog:omit"
+    ],
+    "sort": {
+      "order": "ASC",
+      "on_property": "mergedAt"
+    },
+    "template": "${{CHANGELOG}}\n\n**Full Changelog:** ${{RELEASE_DIFF}}\n",
+    "pr_template": "- ${{TITLE}} (by @${{AUTHOR}} in ${{URL}})${{RELEASE_NOTES}}",
+    "empty_template": "- no changes",
+    "transformers": [
+      {
+        "pattern": "<!--.*-->",
+        "flags": "gus",
+        "target": ""
+      }
+    ],
+    "custom_placeholders": [
+      {
+        "name": "RELEASE_NOTES",
+        "source": "BODY",
+        "transformer": {
+          "pattern": ".*#### Release Notes(?:[\n\\s]|(?:<!--.*?-->))*((?:\\S(?!!--)).*?)[\n\\s]*\n#.*",
+          "flags": "gus",
+          "target": "\n  $1"
+        }
+      }
+    ],
+    "trim_values": false,
+    "max_tags_to_fetch": 200,
+    "max_pull_requests": 500,
+    "max_back_track_time_days": 365
+}
--- a/.github/workflows/release-notes.yml
+++ b/.github/workflows/release-notes.yml
@@ -0,0 +1,51 @@
+# adapted from https://github.com/chipsalliance/chisel/blob/main/.github/workflows/release-notes.yml
+
+name: Generate Release Notes
+
+on:
+  release:
+    types: [created]
+  workflow_dispatch:
+    inputs:
+      toTag:
+        description: 'Tag or ref for which to generate release notes'
+        required: true
+      fromTag:
+        # If you leave this blank, it'll select previous SemVer version
+        # WARNING: Cannot use anything older than a005498 because of the git tree merge
+        description: 'Tag or ref from which to start generating release notes'
+        required: false
+
+
+jobs:
+  generate_release_notes:
+    name: Generate Release Notes
+    runs-on: ubuntu-latest
+
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v3
+      - name: Build Release Notes
+        id: release-notes
+        uses: mikepenz/release-changelog-builder-action@v3.7.0
+        with:
+          configuration: .github/workflows/config/release-notes.json
+          failOnError: true
+          # Amazingly, on release where the inputs are empty, this just does the right thing
+          # The "toTag" is the released tag, and the "fromTag" is the previous tag according to SemVer
+          fromTag: ${{ github.event.inputs.fromTag }}
+          toTag: ${{ github.event.inputs.toTag }}
+          token: ${{ secrets.GITHUB_TOKEN }}
+      - name: Report Release Notes
+        # Put output through env variable to make it robust to quotes
+        env:
+          CHANGELOG: ${{steps.release-notes.outputs.changelog}}
+        run: echo "$CHANGELOG" >> $GITHUB_STEP_SUMMARY
+      - name: Upload Release Notes (on release)
+        if: github.event_name == 'release'
+        uses: softprops/action-gh-release@v0.1.15
+        with:
+          body: ${{ steps.release-notes.outputs.changelog }}
+      - name: Error on uncategorized PRs
+        if: steps.release-notes.outputs.uncategorized_prs != 0
+        run: exit 1
--- a/.github/workflows/require-label.yml
+++ b/.github/workflows/require-label.yml
@@ -0,0 +1,24 @@
+# adapted from https://github.com/chipsalliance/chisel/blob/main/.github/workflows/require-label.yml
+
+name: Require Release Notes Label
+
+on:
+  pull_request:
+    branches:
+      - main
+    types:
+      - opened
+      - synchronize
+      - reopened
+      - labeled
+      - unlabeled
+
+jobs:
+  check_labels:
+    name: Check Labels
+    runs-on: ubuntu-latest
+    steps:
+      - uses: docker://agilepathway/pull-request-label-checker:v1.4.25
+        with:
+          one_of: changelog:added,changelog:changed,changelog:fixed,changelog:omit,changelog:removed
+          repo_token: ${{ secrets.GITHUB_TOKEN }}
--- a/README.md
+++ b/README.md
@@ -23,9 +23,8 @@ Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb
 ## Resources

 * Chipyard Stable Documentation: https://chipyard.readthedocs.io/
-* Chipyard (x FireSim) Tutorial: https://fires.im/tutorial
-* Chipyard Basics slides: https://fires.im/isca22-slides-pdf/02_chipyard_basics.pdf
-* Chipyard Tutorial Exercise slides: https://fires.im/isca22-slides-pdf/03_building_custom_socs.pdf
+* Chipyard (x FireSim) Tutorial: https://fires.im/tutorial-recent/
+* Chipyard Basics slides: https://fires.im/asplos23-slides-pdf/02_chipyard_basics.pdf

 ## Need help?

@@ -74,6 +73,7 @@ These additional publications cover many of the internal components used in Chip
        * **FASED**: D. Biancolin, et al., *FPGA'19*. [PDF](https://people.eecs.berkeley.edu/~biancolin/papers/fased-fpga19.pdf).
        * **Golden Gate**: A. Magyar, et al., *ICCAD'19*. [PDF](https://davidbiancolin.github.io/papers/goldengate-iccad19.pdf).
        * **FirePerf**: S. Karandikar, et al., *ASPLOS'20*. [PDF](https://sagark.org/assets/pubs/fireperf-asplos2020.pdf).
+        * **FireSim ISCA@50 Retrospective**: S. Karandikar, et al., *ISCA@50 Retrospective: 1996-2020*. [PDF](https://sites.coecis.cornell.edu/isca50retrospective/files/2023/06/Karandikar_2018_FireSim.pdf)
 * **Tools**
    * **Chisel**: J. Bachrach, et al., *DAC'12*. [PDF](https://people.eecs.berkeley.edu/~krste/papers/chisel-dac2012.pdf).
    * **FIRRTL**: A. Izraelevitz, et al., *ICCAD'17*. [PDF](https://ieeexplore.ieee.org/document/8203780).
--- a/build.sbt
+++ b/build.sbt
@@ -240,11 +240,7 @@ lazy val nvdla = (project in file("generators/nvdla"))
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "src")
-  .settings(
-    Compile / scalaSource := baseDirectory.value / "main" / "scala" / "barstools" / "iocell",
-    Compile / resourceDirectory := baseDirectory.value / "main" / "resources"
-  )
+lazy val iocell = Project(id = "iocell", base = file("./tools/barstools/") / "iocell")
  .settings(chiselSettings)
  .settings(commonSettings)

--- a/common.mk
+++ b/common.mk
@@ -376,9 +376,7 @@ run-binary-debug: check-binary $(BINARY).run.debug
 run-binaries-debug: check-binaries $(addsuffix .run.debug,$(BINARIES))

 %.run.debug: %.check-exists $(SIM_DEBUG_PREREQ) | $(output_dir)
-ifneq (none,$*)
-	riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump
-endif
+	if [ "$*" != "none" ]; then riscv64-unknown-elf-objdump -D -S $* > $(call get_sim_out_name,$*).dump ; fi
 	(set -o pipefail && $(NUMA_PREFIX) $(sim_debug) $(PERMISSIVE_ON) $(call get_common_sim_flags,$*) $(VERBOSE_FLAGS) $(call get_waveform_flag,$(call get_sim_out_name,$*)) $(PERMISSIVE_OFF) $* </dev/null 2> >(spike-dasm > $(call get_sim_out_name,$*).out) | tee $(call get_sim_out_name,$*).log)

 run-fast: run-asm-tests-fast run-bmark-tests-fast
--- a/docs/Advanced-Concepts/CDEs.rst
+++ b/docs/Advanced-Concepts/CDEs.rst
@@ -21,24 +21,37 @@ Consider the following example using CDEs.

    class WithX(b: Boolean) extends Config((site, here, up) => {
      case SomeKeyX => b
-    }
+    })

    class WithY(b: Boolean) extends Config((site, here, up) => {
      case SomeKeyY => b
-    }
+    })


 When forming a query based on a ``Parameters`` object, like ``p(SomeKeyX)``, the configuration system traverses the "chain" of config fragments until it finds a partial function which is defined at the key, and then returns that value.

 .. code:: scala

-    val params = Config(new WithX(true) ++ new WithY(true)) // "chain" together config fragments
+    val params = new Config(new WithX(true) ++ new WithY(true)) // "chain" together config fragments
    params(SomeKeyX) // evaluates to true
    params(SomeKeyY) // evaluates to true
    params(SomeKeyZ) // evaluates to false

 In this example, the evaluation of ``params(SomeKeyX)`` will terminate in the partial function defined in ``WithX(true)``, while the evaluation of ``params(SomeKeyY)`` will terminate in the partial function defined in ``WithY(true)``. Note that when no partial functions match, the evaluation will return the default value for that parameter.

+Config fragments take precedence from left to right, meaning that a fragment at the start of the chain can override the value of a fragment to the right. It helps to read the fragment chain from right to left.
+
+.. code:: scala
+
+    case object SomeKeyX extends Field[Int](0)
+
+    class WithX(n: Int) extends Config((site, here, up) => {
+      case SomeKeyX => n
+    })
+
+    val params = new Config(new WithX(10) ++ new WithX(5))
+    println(params(SomeKeyX)) // evaluates to 10
+
 The real power of CDEs arises from the ``(site, here, up)`` parameters to the partial functions, which provide useful "views" into the global parameterization that the partial functions may access to determine a parameterization.

 .. note::
@@ -54,10 +67,10 @@ Site

    class WithXEqualsYSite extends Config((site, here, up) => {
      case SomeKeyX => site(SomeKeyY) // expands to site(SomeKeyY, site)
-    }
+    })

-    val params_1 = Config(new WithXEqualsYSite ++ new WithY(true))
-    val params_2 = Config(new WithY(true) ++ new WithXEqualsYSite)
+    val params_1 = new Config(new WithXEqualsYSite ++ new WithY(true))
+    val params_2 = new Config(new WithY(true) ++ new WithXEqualsYSite)
    params_1(SomeKeyX) // evaluates to true
    params_2(SomeKeyX) // evaluates to true

@@ -75,10 +88,10 @@ Here
    class WithXEqualsYHere extends Config((site, here, up) => {
      case SomeKeyY => false
      case SomeKeyX => here(SomeKeyY, site)
-    }
+    })

-    val params_1 = Config(new WithXEqualsYHere ++ new WithY(true))
-    val params_2 = Config(new WithY(true) ++ new WithXEqualsYHere)
+    val params_1 = new Config(new WithXEqualsYHere ++ new WithY(true))
+    val params_2 = new Config(new WithY(true) ++ new WithXEqualsYHere)

    params_1(SomeKeyX) // evaluates to false
    params_2(SomeKeyX) // evaluates to false
@@ -95,10 +108,10 @@ Up

    class WithXEqualsYUp extends Config((site, here, up) => {
      case SomeKeyX => up(SomeKeyY, site)
-    }
+    })

-    val params_1 = Config(new WithXEqualsYUp ++ new WithY(true))
-    val params_2 = Config(new WithY(true) ++ new WithXEqualsYUp)
+    val params_1 = new Config(new WithXEqualsYUp ++ new WithY(true))
+    val params_2 = new Config(new WithY(true) ++ new WithXEqualsYUp)

    params_1(SomeKeyX) // evaluates to true
    params_2(SomeKeyX) // evaluates to false
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -27,15 +27,8 @@ Conda allows users to create an "environment" that holds system dependencies lik

 .. Note:: Chipyard can also run on systems without a Conda installation. However, users on these systems must manually install toolchains and dependencies.

-First, Chipyard requires Conda to be installed on the system.
-Please refer to the `Conda installation instructions <https://github.com/conda-forge/miniforge/#download>`__ on how to install Conda with the **Miniforge** installer.
-Afterwards, verify that Conda is a sufficient version (we test on version 4.12.0 but higher is most likely fine).
-
-.. Note:: If you have installed conda separately from this documentation (i.e. from miniconda or full Anaconda), please ensure you follow https://conda-forge.org/docs/user/introduction.html#how-can-i-install-packages-from-conda-forge to use ``conda-forge`` packages without any issues.
-
-.. code-block:: shell
-
-    conda --version # must be version 22.11.1 or higher
+First, Chipyard requires the latest Conda to be installed on the system.
+Please refer to the `Conda installation instructions <https://github.com/conda-forge/miniforge/#download>`__ on how to install the latest Conda with the **Miniforge** installer.

 After Conda is installed and is on your ``PATH``, we need to install a version of ``git`` to initially checkout the repository.
 For this you can use the system package manager like ``yum`` or ``apt`` to install ``git``.
@@ -71,7 +64,27 @@ Run the following script based off which compiler you would like to use.
 .. Note:: Prior versions of Chipyard recommended ``esp-tools`` for Gemmini development. Gemmini should now be used with the standard ``riscv-tools``.

 .. Warning:: The following script will complete a "full" installation of Chipyard which may take a long time depending on the system.
-    Ensure that this script completes fully (no interruptions) before continuing on.
+    Ensure that this script completes fully (no interruptions) before continuing on. User can use the ``--skip`` or ``-s`` flag to skip steps:
+
+    ``-s 1`` skips initializing Conda environment
+
+    ``-s 2`` skips initializing Chipyard submodules
+
+    ``-s 3`` skips initializing toolchain collateral (Spike, PK, tests, libgloss)
+
+    ``-s 4`` skips initializing ctags
+
+    ``-s 5`` skips pre-compiling Chipyard Scala sources
+
+    ``-s 6`` skips initializing FireSim
+
+    ``-s 7`` skips pre-compiling FireSim sources
+
+    ``-s 8`` skips initializing FireMarshal
+
+    ``-s 9`` skips pre-compiling FireMarshal default buildroot Linux sources
+
+    ``-s 10`` skips running repository clean-up

 .. code-block:: shell

@@ -120,7 +133,7 @@ You can source this file in your ``.bashrc`` or equivalent environment setup fil
    However, it is recommended that the final ``env.sh`` file sourced is the ``env.sh`` located in the
    Chipyard repo that you expect to run ``make`` commands in.

-Pre-built Docker Image
+DEPRECATED: Pre-built Docker Image
 -------------------------------------------

 An alternative to setting up the Chipyard repository locally is to pull the pre-built Docker image from Docker Hub. The image comes with all dependencies installed, Chipyard cloned, and toolchains initialized. This image sets up baseline Chipyard (not including FireMarshal, FireSim, and Hammer initializations). Each image comes with a tag that corresponds to the version of Chipyard cloned/set-up in that image. Not including a tag during the pull will pull the image with the latest version of Chipyard.
--- a/docs/Customization/Custom-Chisel.rst
+++ b/docs/Customization/Custom-Chisel.rst
@@ -52,8 +52,22 @@ Then add ``yourproject`` to the Chipyard top-level build.sbt file.

 You can then import the classes defined in the submodule in a new project if
 you add it as a dependency. For instance, if you want to use this code in
-the ``chipyard`` project, change the final line in build.sbt to the following.
+the ``chipyard`` project, add your project to the list of sub-projects in the 
+`.dependsOn()` for `lazy val chipyard`. The original code may change over time, but it
+should look something like this:

 .. code-block:: scala

-    lazy val chipyard = (project in file(".")).settings(commonSettings).dependsOn(testchipip, yourproject)
+    lazy val chipyard = (project in file("generators/chipyard"))
+        .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+            sha3, dsptools, `rocket-dsp-utils`,
+            gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
+            yourproject, // <- added to the middle of the list for simplicity
+            constellation, mempress)
+        .settings(libraryDependencies ++= rocketLibDeps.value)
+        .settings(
+            libraryDependencies ++= Seq(
+            "org.reflections" % "reflections" % "0.10.2"
+            )
+        )
+        .settings(commonSettings)
--- a/docs/Customization/Memory-Hierarchy.rst
+++ b/docs/Customization/Memory-Hierarchy.rst
@@ -94,7 +94,7 @@ memory channel.

 Instead of connecting to off-chip DRAM, you can instead connect a scratchpad
 and remove the off-chip link. This is done by adding a fragment like
-``testchipip.WithBackingScratchpad`` to your configuration and removing the
+``testchipip.WithScratchpad`` to your configuration and removing the
 memory port with ``freechips.rocketchip.subsystem.WithNoMemPort``.

 .. literalinclude:: ../../generators/chipyard/src/main/scala/config/RocketConfigs.scala
--- a/docs/VLSI/ASAP7-Tutorial.rst
+++ b/docs/VLSI/ASAP7-Tutorial.rst
@@ -66,6 +66,12 @@ In the Chipyard root, ensure that you have the Chipyard conda environment activa

 to pull and install the plugin submodules. Note that for technologies other than ``sky130`` or ``asap7``, the tech submodule must be added in the ``vlsi`` folder first.

+Now navigate to the ``vlsi`` directory. The remainder of the tutorial will assume you are in this directory.
+
+.. code-block:: shell
+
+    cd ~chipyard/vlsi
+
 Building the Design
 --------------------
 To elaborate the ``TinyRocketConfig`` and set up all prerequisites for the build system to push the design and SRAM macros through the flow:
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -22,12 +22,14 @@ class WithNoDesignKey extends Config((site, here, up) => {
 })

 class WithArty100TTweaks extends Config(
-  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
  new WithArty100TUARTTSI ++
  new WithArty100TDDRTL ++
  new WithNoDesignKey ++
+  new testchipip.WithUARTTSIClient ++
+  new chipyard.harness.WithSerialTLTiedOff ++
  new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
  new chipyard.config.WithMemoryBusFrequency(50.0) ++
+  new chipyard.config.WithFrontBusFrequency(50.0) ++
  new chipyard.config.WithSystemBusFrequency(50.0) ++
  new chipyard.config.WithPeripheryBusFrequency(50.0) ++
  new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
--- a/fpga/src/main/scala/arty100t/HarnessBinders.scala
+++ b/fpga/src/main/scala/arty100t/HarnessBinders.scala
@@ -21,29 +21,17 @@ import chipyard.iobinders.JTAGChipIO
 import testchipip._

 class WithArty100TUARTTSI(uartBaudRate: BigInt = 115200) extends OverrideHarnessBinder({
-  (system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
+  (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    require(ports.size <= 1)
+    val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
    ports.map({ port =>
-      val ath = th.asInstanceOf[LazyRawModuleImp].wrapper.asInstanceOf[Arty100THarness]
-      val freq = p(PeripheryBusKey).dtsFrequency.get
-      val bits = port.bits
-      port.clock := th.harnessBinderClock
-      val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
-      val uart_to_serial = Module(new UARTToSerial(
-        freq, UARTParams(0, initBaudRate=uartBaudRate)))
-      val serial_width_adapter = Module(new SerialWidthAdapter(
-        narrowW = 8, wideW = TSI.WIDTH))
-      serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
-
-      ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
-
-      ath.io_uart_bb.bundle <> uart_to_serial.io.uart
-      ath.other_leds(1) := uart_to_serial.io.dropped
-
-      ath.other_leds(9) := ram.module.io.tsi2tl_state(0)
-      ath.other_leds(10) := ram.module.io.tsi2tl_state(1)
-      ath.other_leds(11) := ram.module.io.tsi2tl_state(2)
-      ath.other_leds(12) := ram.module.io.tsi2tl_state(3)
+      ath.io_uart_bb.bundle <> port.uart
+      ath.other_leds(1) := port.dropped
+      ath.other_leds(9) := port.tsi2tl_state(0)
+      ath.other_leds(10) := port.tsi2tl_state(1)
+      ath.other_leds(11) := port.tsi2tl_state(2)
+      ath.other_leds(12) := port.tsi2tl_state(3)
    })
  }
 })
--- a/generators/boom
+++ b/generators/boom
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.devices.tilelink._

 // DOC include start: DigitalTop
 class DigitalTop(implicit p: Parameters) extends ChipyardSystem
+  with testchipip.CanHavePeripheryUARTTSI // Enables optional UART-based TSI transport
  with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
  with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
  with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
--- a/generators/chipyard/src/main/scala/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/IOBinders.scala
@@ -303,6 +303,15 @@ class WithSerialTLIOCells extends OverrideIOBinder({
  }).getOrElse((Nil, Nil))
 })

+class WithSerialTLPunchthrough extends OverrideIOBinder({
+  (system: CanHavePeripheryTLSerial) => system.serial_tl.map({ s =>
+    val sys = system.asInstanceOf[BaseSubsystem]
+    val port = IO(s.getWrappedValue.cloneType)
+    port <> s.getWrappedValue
+    (Seq(port), Nil)
+  }).getOrElse((Nil, Nil))
+})
+
 class WithAXI4MemPunchthrough extends OverrideLazyIOBinder({
  (system: CanHaveMasterAXI4MemPort) => {
    implicit val p: Parameters = GetSystemParameters(system)
@@ -411,6 +420,15 @@ class WithCustomBootPin extends OverrideIOBinder({
  }).getOrElse((Nil, Nil))
 })

+class WithUARTTSIPunchthrough extends OverrideIOBinder({
+  (system: CanHavePeripheryUARTTSI) => system.uart_tsi.map({ p =>
+    val sys = system.asInstanceOf[BaseSubsystem]
+    val uart_tsi = IO(new UARTTSIIO(p.uartParams))
+    uart_tsi <> p
+    (Seq(uart_tsi), Nil)
+  }).getOrElse((Nil, Nil))
+})
+
 class WithTLMemPunchthrough extends OverrideIOBinder({
  (system: CanHaveMasterTLMemPort) => {
    val io_tl_mem_pins_temp = IO(DataMirror.internal.chiselTypeClone[HeterogeneousBag[TLBundle]](system.mem_tl)).suggestName("tl_slave")
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -38,9 +38,9 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
    val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
    val pllCtrl       = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl    (baseAddress + 0x40000, tlbus.beatBytes)) }

-    clockDivider.tlNode  := system.prci_ctrl_bus
-    clockSelector.tlNode := system.prci_ctrl_bus
-    pllCtrl.tlNode       := system.prci_ctrl_bus
+    clockDivider.tlNode  := system.prci_ctrl_bus.get
+    clockSelector.tlNode := system.prci_ctrl_bus.get
+    pllCtrl.tlNode       := system.prci_ctrl_bus.get

    system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode

--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -14,14 +14,17 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.prci._

-import testchipip.{TLTileResetCtrl}
+import testchipip.{TLTileResetCtrl, ClockGroupFakeResetSynchronizer}

 case class ChipyardPRCIControlParams(
  slaveWhere: TLBusWrapperLocation = CBUS,
  baseAddress: BigInt = 0x100000,
  enableTileClockGating: Boolean = true,
-  enableTileResetSetting: Boolean = true
-)
+  enableTileResetSetting: Boolean = true,
+  enableResetSynchronizers: Boolean = true // this should only be disabled to work around verilator async-reset initialization problems
+) {
+  def generatePRCIXBar = enableTileClockGating || enableTileResetSetting
+}


 case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
@@ -36,13 +39,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
  val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
  prci_ctrl_domain.clockNode := tlbus.fixedClockNode

-  val prci_ctrl_bus = prci_ctrl_domain { TLXbar() }
-  tlbus.coupleTo("prci_ctrl") { (prci_ctrl_bus
+  val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
+  prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
    := TLFIFOFixer(TLFIFOFixer.all)
    := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes)
    := TLBuffer()
    := _)
-  }
+  })

  // Aggregate all the clock groups into a single node
  val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
@@ -79,19 +82,40 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
  // diplomatic IOBinder should drive
  val frequencySpecifier = ClockGroupFrequencySpecifier(p(ClockFrequencyAssignersKey))
  val clockGroupCombiner = ClockGroupCombiner()
-  val resetSynchronizer  = prci_ctrl_domain { ClockGroupResetSynchronizer() }
+  val resetSynchronizer  = prci_ctrl_domain {
+    if (prciParams.enableResetSynchronizers) ClockGroupResetSynchronizer() else ClockGroupFakeResetSynchronizer()
+  }
  val tileClockGater     = Option.when(prciParams.enableTileClockGating) { prci_ctrl_domain {
    val clock_gater = LazyModule(new TileClockGater(prciParams.baseAddress + 0x00000, tlbus.beatBytes))
-    clock_gater.tlNode := prci_ctrl_bus
+    clock_gater.tlNode := prci_ctrl_bus.get
    clock_gater
  } }
  val tileResetSetter    = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
    val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
      tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
-    reset_setter.tlNode := prci_ctrl_bus
+    reset_setter.tlNode := prci_ctrl_bus.get
    reset_setter
  } }

+  if (!prciParams.enableResetSynchronizers) {
+    println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+DISABLING THE RESET SYNCHRONIZERS RESULTS IN
+A BROKEN DESIGN THAT WILL NOT BEHAVE
+PROPERLY AS ASIC OR FPGA.
+
+THESE SHOULD ONLY BE DISABLED TO WORK AROUND
+LIMITATIONS IN ASYNC RESET INITIALIZATION IN
+RTL SIMULATORS, NAMELY VERILATOR.
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+  }
+
  (aggregator
    := frequencySpecifier
    := clockGroupCombiner
--- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
@@ -13,23 +13,6 @@ import freechips.rocketchip.util.ElaborationArtefacts

 import testchipip._

-object ResetStretcher {
-  def apply(clock: Clock, reset: Reset, cycles: Int): Reset = {
-    withClockAndReset(clock, reset) {
-      val n = log2Ceil(cycles)
-      val count = Module(new AsyncResetRegVec(w=n, init=0))
-      val resetout = Module(new AsyncResetRegVec(w=1, init=1))
-      count.io.en := resetout.io.q
-      count.io.d := count.io.q + 1.U
-      resetout.io.en := resetout.io.q
-      resetout.io.d := count.io.q < (cycles-1).U
-
-      resetout.io.q.asBool
-    }
-  }
-}
-
-
 case class ClockSelNode()(implicit valName: ValName)
  extends MixedNexusNode(ClockImp, ClockGroupImp)(
     dFn = { d => ClockGroupSourceParameters() },
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -22,25 +22,29 @@ class AbstractConfig extends Config(
  new chipyard.harness.WithTieOffInterrupts ++                     // tie-off interrupt ports, if present
  new chipyard.harness.WithTieOffL2FBusAXI ++                      // tie-off external AXI4 master, if present
  new chipyard.harness.WithCustomBootPinPlusArg ++                 // drive custom-boot pin with a plusarg, if custom-boot-pin is present
+  new chipyard.harness.WithSimUARTToUARTTSI ++                     // connect a SimUART to the UART-TSI port
  new chipyard.harness.WithClockAndResetFromHarness ++             // all Clock/Reset I/O in ChipTop should be driven by harnessClockInstantiator
  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz

  // The IOBinders instantiate ChipTop IOs to match desired digital IOs
-  // IOCells are generated for "Chip-like" IOs, while simulation-only IOs are directly punched through
+  // IOCells are generated for "Chip-like" IOs
+  new chipyard.iobinders.WithSerialTLIOCells ++
+  new chipyard.iobinders.WithDebugIOCells ++
+  new chipyard.iobinders.WithUARTIOCells ++
+  new chipyard.iobinders.WithGPIOCells ++
+  new chipyard.iobinders.WithSPIIOCells ++
+  new chipyard.iobinders.WithExtInterruptIOCells ++
+  new chipyard.iobinders.WithCustomBootPin ++
+  // The "punchthrough" IOBInders below don't generate IOCells, as these interfaces shouldn't really be mapped to ASIC IO
+  // Instead, they directly pass through the DigitalTop ports to ports in the ChipTop
  new chipyard.iobinders.WithAXI4MemPunchthrough ++
  new chipyard.iobinders.WithAXI4MMIOPunchthrough ++
  new chipyard.iobinders.WithTLMemPunchthrough ++
  new chipyard.iobinders.WithL2FBusAXI4Punchthrough ++
  new chipyard.iobinders.WithBlockDeviceIOPunchthrough ++
  new chipyard.iobinders.WithNICIOPunchthrough ++
-  new chipyard.iobinders.WithSerialTLIOCells ++
-  new chipyard.iobinders.WithDebugIOCells ++
-  new chipyard.iobinders.WithUARTIOCells ++
-  new chipyard.iobinders.WithGPIOCells ++
-  new chipyard.iobinders.WithSPIIOCells ++
  new chipyard.iobinders.WithTraceIOPunchthrough ++
-  new chipyard.iobinders.WithExtInterruptIOCells ++
-  new chipyard.iobinders.WithCustomBootPin ++
+  new chipyard.iobinders.WithUARTTSIPunchthrough ++

  // By default, punch out IOs to the Harness
  new chipyard.clocking.WithPassthroughClockGenerator ++
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -2,30 +2,38 @@ package chipyard

 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.{MBUS, SBUS}
+import testchipip.{OBUS}

 // A simple config demonstrating how to set up a basic chip in Chipyard
-class ChipLikeQuadRocketConfig extends Config(
+class ChipLikeRocketConfig extends Config(
  //==================================
  // Set up TestHarness
  //==================================
  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute frequencies for simulations in the harness
                                                                   // NOTE: This only simulates properly in VCS
+  new chipyard.harness.WithSimAXIMemOverSerialTL ++                // Attach SimDRAM to serial-tl port

  //==================================
  // Set up tiles
  //==================================
  new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++    // Add rational crossings between RocketTile and uncore
-  new freechips.rocketchip.subsystem.WithNBigCores(4) ++                     // quad-core (4 RocketTiles)
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++                     // 1 RocketTile

  //==================================
  // Set up I/O
  //==================================
  new testchipip.WithSerialTLWidth(4) ++
  new testchipip.WithSerialTLBackingMemory ++                                           // Backing memory is over serial TL protocol
-  new chipyard.harness.WithSimAXIMemOverSerialTL ++                                     // Attach fast SimDRAM to TestHarness
  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++                  // 4GB max external memory
  new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++                          // 1 memory channel

+  //==================================
+  // Set up buses
+  //==================================
+  new testchipip.WithOffchipBusClient(MBUS) ++
+  new testchipip.WithOffchipBus ++
+
  //==================================
  // Set up clock./reset
  //==================================
@@ -36,3 +44,64 @@ class ChipLikeQuadRocketConfig extends Config(

  new chipyard.config.AbstractConfig)

+// A simple config demonstrating a "bringup prototype" to bringup the ChipLikeRocketconfig
+class ChipBringupHostConfig extends Config(
+  //=============================
+  // Set up TestHarness for standalone-sim
+  //=============================
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++  // Generate absolute frequencies
+  new chipyard.harness.WithSerialTLTiedOff ++                       // when doing standalone sim, tie off the serial-tl port
+  new chipyard.harness.WithSimTSIToUARTTSI ++                       // Attach SimTSI-over-UART to the UART-TSI port
+  new chipyard.iobinders.WithSerialTLPunchthrough ++                // Don't generate IOCells for the serial TL (this design maps to FPGA)
+
+  //=============================
+  // Setup the SerialTL side on the bringup device
+  //=============================
+  new testchipip.WithSerialTLWidth(4) ++                                       // match width with the chip
+  new testchipip.WithSerialTLMem(base = 0x0, size = 0x80000000L,               // accessible memory of the chip that doesn't come from the tethered host
+                                 idBits = 4, isMainMemory = false) ++          // This assumes off-chip mem starts at 0x8000_0000
+  new testchipip.WithSerialTLClockDirection(provideClockFreqMHz = Some(75)) ++ // bringup board drives the clock for the serial-tl receiver on the chip, use 75MHz clock
+
+  //============================
+  // Setup bus topology on the bringup system
+  //============================
+  new testchipip.WithOffchipBusClient(SBUS,                                    // offchip bus hangs off the SBUS
+    blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly
+  new testchipip.WithOffchipBus ++                                             // offchip bus
+
+  //=============================
+  // Set up memory on the bringup system
+  //=============================
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++         // match what the chip believes the max size should be
+
+  //=============================
+  // Generate the TSI-over-UART side of the bringup system
+  //=============================
+  new testchipip.WithUARTTSIClient(initBaudRate = BigInt(921600)) ++           // nonstandard baud rate to improve performance
+
+  //=============================
+  // Set up clocks of the bringup system
+  //=============================
+  new chipyard.clocking.WithPassthroughClockGenerator ++ // pass all the clocks through, since this isn't a chip
+  new chipyard.config.WithFrontBusFrequency(75.0) ++     // run all buses of this system at 75 MHz
+  new chipyard.config.WithMemoryBusFrequency(75.0) ++
+  new chipyard.config.WithPeripheryBusFrequency(75.0) ++
+
+  // Base is the no-cores config
+  new chipyard.NoCoresConfig)
+
+class TetheredChipLikeRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++   // use absolute freqs for sims in the harness
+  new chipyard.harness.WithMultiChipSerialTL(0, 1) ++                // connect the serial-tl ports of the chips together
+  new chipyard.harness.WithMultiChip(0, new ChipLikeRocketConfig) ++
+  new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
+
+
+// Verilator does not initialize some of the async-reset reset-synchronizer
+// flops properly, so this config disables them.
+// This config should only be used for verilator simulations
+class VerilatorCITetheredChipLikeRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++   // use absolute freqs for sims in the harness
+  new chipyard.harness.WithMultiChipSerialTL(0, 1) ++                // connect the serial-tl ports of the chips together
+  new chipyard.harness.WithMultiChip(0, new chipyard.config.WithNoResetSynchronizers ++ new ChipLikeRocketConfig) ++
+  new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
--- a/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/NoCoreConfigs.scala
@@ -4,6 +4,15 @@ import org.chipsalliance.cde.config.{Config}

 // A empty config with no cores. Useful for testing
 class NoCoresConfig extends Config(
+  new testchipip.WithNoBootAddrReg ++
+  new testchipip.WithNoCustomBootPin ++
+  new chipyard.config.WithNoCLINT ++
+  new chipyard.config.WithNoBootROM ++
+  new chipyard.config.WithBroadcastManager ++
+  new chipyard.config.WithNoUART ++
+  new chipyard.config.WithNoTileClockGaters ++
+  new chipyard.config.WithNoTileResetSetters ++
+  new chipyard.config.WithNoBusErrorDevices ++
  new chipyard.config.WithNoDebug ++
  new chipyard.config.WithNoPLIC ++
  new chipyard.config.AbstractConfig)
--- a/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
@@ -2,6 +2,7 @@ package chipyard

 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.subsystem.{MBUS}

 // ---------------------------------------------------------
 // Configs which add non-default peripheral devices or ports
@@ -65,13 +66,15 @@ class dmiRocketConfig extends Config(
 // DOC include end: DmiRocket

 class ManyPeripheralsRocketConfig extends Config(
+  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
+  new testchipip.WithOffchipBusClient(MBUS) ++               // OBUS provides backing memory to the MBUS
+  new testchipip.WithOffchipBus ++                           // OBUS must exist for serial-tl to master off-chip memory
+  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
  new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
  new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice
  new chipyard.config.WithSPIFlash ++                        // add the SPI flash controller
  new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++  // add default external master port
  new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
-  new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
-  new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
  new freechips.rocketchip.subsystem.WithNoMemPort ++        // remove AXI4 backing memory
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)
@@ -80,3 +83,13 @@ class QuadChannelRocketConfig extends Config(
  new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++      // 4 AXI4 channels
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)
+
+class UARTTSIRocketConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++
+  new testchipip.WithUARTTSIClient ++
+  new chipyard.config.WithMemoryBusFrequency(10) ++
+  new chipyard.config.WithFrontBusFrequency(10) ++
+  new chipyard.config.WithPeripheryBusFrequency(10) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
+  new chipyard.config.AbstractConfig)
+
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -19,14 +19,6 @@ class TinyRocketConfig extends Config(
  new freechips.rocketchip.subsystem.With1TinyCore ++             // single tiny rocket-core
  new chipyard.config.AbstractConfig)

-class UARTTSIRocketConfig extends Config(
-  new chipyard.harness.WithUARTSerial ++
-  new chipyard.config.WithNoUART ++
-  new chipyard.config.WithMemoryBusFrequency(10) ++
-  new chipyard.config.WithPeripheryBusFrequency(10) ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++         // single rocket-core
-  new chipyard.config.AbstractConfig)
-
 class SimAXIRocketConfig extends Config(
  new chipyard.harness.WithSimAXIMem ++                     // drive the master AXI4 memory with a SimAXIMem, a 1-cycle magic memory, instead of default SimDRAM
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -106,3 +106,15 @@ class WithControlBusFrequency(freqMHz: Double) extends Config((site, here, up) =

 class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
 class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
+
+class WithNoTileClockGaters extends Config((site, here, up) => {
+  case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileClockGating = false)
+})
+
+class WithNoTileResetSetters extends Config((site, here, up) => {
+  case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileResetSetting = false)
+})
+
+class WithNoResetSynchronizers extends Config((site, here, up) => {
+  case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
+})
--- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
@@ -5,7 +5,7 @@ import chisel3._
 import chisel3.util.{log2Up}

 import org.chipsalliance.cde.config.{Config}
-import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey}
+import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
 import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI}
 import freechips.rocketchip.stage.phases.TargetDirKey
 import freechips.rocketchip.subsystem._
@@ -75,3 +75,19 @@ class WithNoPLIC extends Config((site, here, up) => {
 class WithDebugModuleAbstractDataWords(words: Int = 16) extends Config((site, here, up) => {
  case DebugModuleKey => up(DebugModuleKey).map(_.copy(nAbstractDataWords=words))
 })
+
+class WithNoCLINT extends Config((site, here, up) => {
+  case CLINTKey => None
+})
+
+class WithNoBootROM extends Config((site, here, up) => {
+  case BootROMLocated(_) => None
+})
+
+class WithNoBusErrorDevices extends Config((site, here, up) => {
+  case SystemBusKey => up(SystemBusKey).copy(errorDevice = None)
+  case ControlBusKey => up(ControlBusKey).copy(errorDevice = None)
+  case PeripheryBusKey => up(PeripheryBusKey).copy(errorDevice = None)
+  case MemoryBusKey => up(MemoryBusKey).copy(errorDevice = None)
+  case FrontBusKey => up(FrontBusKey).copy(errorDevice = None)
+})
--- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala
@@ -30,9 +30,7 @@ import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvon

 import scala.reflect.{ClassTag}

-case object HarnessBinders extends Field[Map[String, (Any, HasHarnessInstantiators, Seq[Data]) => Unit]](
-  Map[String, (Any, HasHarnessInstantiators, Seq[Data]) => Unit]().withDefaultValue((t: Any, th: HasHarnessInstantiators, d: Seq[Data]) => ())
-)
+case object HarnessBinders extends Field[HarnessBinderMap](HarnessBinderMapDefault)

 object ApplyHarnessBinders {
  def apply(th: HasHarnessInstantiators, sys: LazyModule, portMap: Map[String, Seq[Data]])(implicit p: Parameters): Unit = {
@@ -51,12 +49,8 @@ class HarnessBinder[T, S <: HasHarnessInstantiators, U <: Data](composer: ((T, S
        val pts = ports.collect({case p: U => p})
        require (pts.length == ports.length, s"Port type mismatch between IOBinder and HarnessBinder: ${portTag}")
        val upfn = up(HarnessBinders, site)(systemTag.runtimeClass.toString)
-        th match {
-          case th: S =>
-            t match {
-              case system: T => composer(upfn)(system, th, pts)
-              case _ =>
-            }
+        (th, t) match {
+          case (th: S, system: T) => composer(upfn)(system, th, pts)
          case _ =>
        }
      })
@@ -296,7 +290,9 @@ class WithSerialTLTiedOff extends OverrideHarnessBinder({
    implicit val p = chipyard.iobinders.GetSystemParameters(system)
    ports.map({ port =>
      val bits = port.bits
-      port.clock := false.B.asClock
+      if (DataMirror.directionOf(port.clock) == Direction.Input) {
+        port.clock := false.B.asClock
+      }
      port.bits.out.ready := false.B
      port.bits.in.valid := false.B
      port.bits.in.bits := DontCare
@@ -317,21 +313,34 @@ class WithSimTSIOverSerialTL extends OverrideHarnessBinder({
  }
 })

-class WithUARTSerial extends OverrideHarnessBinder({
-  (system: CanHavePeripheryTLSerial, th: HasHarnessInstantiators, ports: Seq[ClockedIO[SerialIO]]) => {
+class WithSimUARTToUARTTSI extends OverrideHarnessBinder({
+  (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    require(ports.size <= 1)
+    ports.map { port => {
+      UARTAdapter.connect(Seq(port.uart),
+        baudrate=port.uartParams.initBaudRate,
+        clockFrequency=th.getHarnessBinderClockFreqHz.toInt,
+        forcePty=true)
+      assert(!port.dropped)
+    }}
+  }
+})
+
+class WithSimTSIToUARTTSI extends OverrideHarnessBinder({
+  (system: CanHavePeripheryUARTTSI, th: HasHarnessInstantiators, ports: Seq[UARTTSIIO]) => {
+    implicit val p = chipyard.iobinders.GetSystemParameters(system)
+    require(ports.size <= 1)
    ports.map({ port =>
-      val freq = p(PeripheryBusKey).dtsFrequency.get
-      val bits = port.bits
-      port.clock := th.harnessBinderClock
-      val ram = TSIHarness.connectRAM(system.serdesser.get, bits, th.harnessBinderReset)
-      val uart_to_serial = Module(new UARTToSerial(freq, UARTParams(0)))
-      val serial_width_adapter = Module(new SerialWidthAdapter(
-        8, TSI.WIDTH))
-      ram.module.io.tsi.flipConnect(serial_width_adapter.io.wide)
-      UARTAdapter.connect(Seq(uart_to_serial.io.uart), uart_to_serial.div)
+      val freq = th.getHarnessBinderClockFreqHz.toInt
+      val uart_to_serial = Module(new UARTToSerial(freq, port.uartParams))
+      val serial_width_adapter = Module(new SerialWidthAdapter(8, TSI.WIDTH))
+      val success = SimTSI.connect(Some(TSIIO(serial_width_adapter.io.wide)), th.harnessBinderClock, th.harnessBinderReset)
+      when (success) { th.success := true.B }
+      assert(!uart_to_serial.io.dropped)
      serial_width_adapter.io.narrow.flipConnect(uart_to_serial.io.serial)
-      th.success := false.B
+      uart_to_serial.io.uart.rxd := port.uart.txd
+      port.uart.rxd := uart_to_serial.io.uart.txd
    })
  }
 })
@@ -385,7 +394,7 @@ class WithClockAndResetFromHarness extends OverrideHarnessBinder({
        val clock = th.harnessClockInstantiator.requestClockMHz(s"clock_${c.freqMHz.toInt}MHz", c.freqMHz)
        c.clock := clock
      }
-      case r: AsyncReset => r := th.harnessBinderReset.asAsyncReset
+      case r: AsyncReset => r := th.referenceReset.asAsyncReset
    })
  }
 })
--- a/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
+++ b/generators/chipyard/src/main/scala/harness/HasHarnessInstantiators.scala
@@ -86,6 +86,7 @@ trait HasHarnessInstantiators {
        case (d: HasIOBinders, i: Int) => ApplyHarnessBinders(this, d.lazySystem, d.portMap)(chipParameters(i))
        case _ =>
      }
+      ApplyMultiHarnessBinders(this, lazyDuts)
    }

    val harnessBinderClk = harnessClockInstantiator.requestClockMHz("harnessbinder_clock", getHarnessBinderClockFreqMHz)
--- a/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
+++ b/generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala
@@ -0,0 +1,78 @@
+package chipyard.harness
+
+import chisel3._
+import chisel3.util._
+
+import org.chipsalliance.cde.config.{Field, Config, Parameters}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImpLike}
+import freechips.rocketchip.devices.debug._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
+
+import testchipip._
+
+import chipyard._
+import chipyard.clocking.{HasChipyardPRCI, ClockWithFreq}
+import chipyard.iobinders.{GetSystemParameters, JTAGChipIO, HasIOBinders}
+
+import scala.reflect.{ClassTag}
+
+case class MultiHarnessBinders(c0: Int, c1: Int) extends Field[MultiHarnessBinderMap](MultiHarnessBinderMapDefault)
+
+class MultiHarnessBinder[T0, T1, S <: HasHarnessInstantiators, U0 <: Data, U1 <: Data]
+  (chip0: Int, chip1: Int, fn: => (T0, T1, S, Seq[U0], Seq[U1]) => Unit)
+  (implicit tag0: ClassTag[T0], tag1: ClassTag[T1], thtag: ClassTag[S], ptag0: ClassTag[U0], ptag1: ClassTag[U1])
+    extends Config((site, here, up) => {
+      // Override any HarnessBinders for chip0/chip1
+      case MultiChipParameters(`chip0`) => new Config(
+        new OverrideHarnessBinder[T0, S, U0]((system: T0, th: S, ports: Seq[U0]) => Nil) ++
+        up(MultiChipParameters(chip0))
+      )
+      case MultiChipParameters(`chip1`) => new Config(
+        new OverrideHarnessBinder[T1, S, U1]((system: T1, th: S, ports: Seq[U1]) => Nil) ++
+        up(MultiChipParameters(chip1))
+      )
+      // Set the multiharnessbinder key
+      case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) +
+        ((tag0.runtimeClass.toString, tag1.runtimeClass.toString) ->
+          ((c0: Any, c1: Any, th: HasHarnessInstantiators, ports0: Seq[Data], ports1: Seq[Data]) => {
+            val pts0 = ports0.map(_.asInstanceOf[U0])
+            val pts1 = ports1.map(_.asInstanceOf[U1])
+            require(pts0.size == pts1.size)
+            (c0, c1, th) match {
+              case (c0: T0, c1: T1, th: S) => fn(c0, c1, th, pts0, pts1)
+              case _ =>
+            }
+          })
+      )
+    })
+
+object ApplyMultiHarnessBinders {
+  def apply(th: HasHarnessInstantiators, chips: Seq[LazyModule])(implicit p: Parameters): Unit = {
+    Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) {
+      (chips(i), chips(j)) match {
+        case (l0: HasIOBinders, l1: HasIOBinders) => p(MultiHarnessBinders(i, j)).foreach {
+          case ((s0, s1), f) => {
+            f(l0.lazySystem       , l1.lazySystem       , th, l0.portMap(s0), l1.portMap(s1))
+            f(l0.lazySystem.module, l1.lazySystem.module, th, l0.portMap(s0), l1.portMap(s1))
+          }
+        }
+        case _ =>
+      }
+    }}
+  }
+}
+
+class WithMultiChipSerialTL(chip0: Int, chip1: Int) extends MultiHarnessBinder(chip0, chip1, (
+  (system0: CanHavePeripheryTLSerial, system1: CanHavePeripheryTLSerial,
+    th: HasHarnessInstantiators,
+    ports0: Seq[ClockedIO[SerialIO]], ports1: Seq[ClockedIO[SerialIO]]
+  ) => {
+    require(ports0.size == ports1.size)
+    (ports0 zip ports1).map { case (l, r) =>
+      l.clock <> r.clock
+      require(l.bits.w == r.bits.w)
+      l.bits.flipConnect(r.bits)
+    }
+  }
+))
--- a/generators/chipyard/src/main/scala/harness/package.scala
+++ b/generators/chipyard/src/main/scala/harness/package.scala
@@ -0,0 +1,17 @@
+package chipyard
+
+import chisel3._
+import scala.collection.immutable.ListMap
+
+package object harness
+{
+  type HarnessBinderFunction = (Any, HasHarnessInstantiators, Seq[Data]) => Unit
+  type HarnessBinderMap = Map[String, HarnessBinderFunction]
+  def HarnessBinderMapDefault: HarnessBinderMap = (new ListMap[String, HarnessBinderFunction])
+    .withDefaultValue((t: Any, th: HasHarnessInstantiators, d: Seq[Data]) => ())
+
+  type MultiHarnessBinderFunction = (Any, Any, HasHarnessInstantiators, Seq[Data], Seq[Data]) => Unit
+  type MultiHarnessBinderMap = Map[(String, String), MultiHarnessBinderFunction]
+  def MultiHarnessBinderMapDefault: MultiHarnessBinderMap = (new ListMap[(String, String), MultiHarnessBinderFunction])
+    .withDefaultValue((_: Any, _: Any, _: HasHarnessInstantiators, _: Seq[Data], _: Seq[Data]) => ())
+}
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/sims/firesim
+++ b/sims/firesim
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -32,7 +32,7 @@ include $(base_dir)/sims/common-sim-flags.mk

 # If verilator seed unspecified, verilator uses srand as random seed
 ifdef RANDOM_SEED
-SEED_FLAG=+verilator+seed+I$(RANDOM_SEED)
+SEED_FLAG=+verilator+seed+$(RANDOM_SEED)
 else
 SEED_FLAG=
 endif
--- a/tools/barstools
+++ b/tools/barstools
--- a/vlsi/example-designs/sky130-commercial.yml
+++ b/vlsi/example-designs/sky130-commercial.yml
@@ -16,4 +16,4 @@ vlsi.inputs.clocks: [
 #     - path: "ChipTop"
 #       ...
 #       margins:
-#         right: 0  # or left: 0
+#         right: 0  # or left: 0
--- a/vlsi/example-designs/sky130-openroad-rockettile.yml
+++ b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -1,7 +1,7 @@
 # Override configurations in ../example-sky130.yml and example-designs

 # Specify clock signals
-# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
 vlsi.inputs.clocks: [
  {name: "clock", period: "30ns", uncertainty: "3ns"}
 ]
--- a/vlsi/example-designs/sky130-rocket.yml
+++ b/vlsi/example-designs/sky130-rocket.yml
@@ -1,7 +1,7 @@
 # Override configurations in ../example-sky130.yml and example-designs

 # Specify clock signals
-# Rocket/RocketTile names clock signal "clock" instead of "clock_clock"
+# Rocket/RocketTile names clock signal "clock" instead of "clock_uncore_clock"
 vlsi.inputs.clocks: [
  {name: "clock", period: "5ns", uncertainty: "1ns"}
 ]