Merge pull request #719 from ucb-bar/local-chisel34

Chisel 3.4, FIRRTL 1.4 and Rocket Chip November Bump
2020-12-13 11:12:20 -07:00
parent 70d41996dd 02f22e0061
commit 6c85ed4b34
35 changed files with 296 additions and 228 deletions
--- a/.circleci/defaults.sh
+++ b/.circleci/defaults.sh
@@ -33,8 +33,9 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install
 REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
 REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
 REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
+REMOTE_JAVA_OPTS="-Xmx10G -Xss8M"
 # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI
-REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
+REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
 REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install

 # local variables (aka within the docker container)
--- a/.circleci/do-rtl-build.sh
+++ b/.circleci/do-rtl-build.sh
@@ -63,7 +63,7 @@ do
         export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
         export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
         export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-         make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}"
+         make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}"
 done

 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
--- a/.circleci/run-firesim-scala-tests.sh
+++ b/.circleci/run-firesim-scala-tests.sh
@@ -49,4 +49,4 @@ run "export RISCV=\"$TOOLS_DIR\"; \
     export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
     export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
     export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-     make -C $REMOTE_FIRESIM_DIR JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" testOnly ${mapping[$1]}"
+     make -C $REMOTE_FIRESIM_DIR JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" testOnly ${mapping[$1]}"
--- a/.gitignore
+++ b/.gitignore
@@ -19,4 +19,4 @@ tags
 *~
 env-riscv-tools.sh
 env-esp-tools.sh
-.bloop/
+.bsp/
--- a/.gitmodules
+++ b/.gitmodules
@@ -76,7 +76,7 @@
 	url = https://github.com/ucb-bar/dsptools.git
 [submodule "tools/chisel-testers"]
 	path = tools/chisel-testers
-	url = https://github.com/freechipsproject/chisel-testers.git
+	url = https://github.com/ucb-bar/chisel-testers.git
 [submodule "tools/treadle"]
 	path = tools/treadle
 	url = https://github.com/freechipsproject/treadle.git
--- a/build.sbt
+++ b/build.sbt
@@ -1,30 +1,34 @@
 import Tests._

-// This gives us a nicer handle  to the root project instead of using the
+// This gives us a nicer handle to the root project instead of using the
 // implicit one
 lazy val chipyardRoot = Project("chipyardRoot", file("."))

 lazy val commonSettings = Seq(
  organization := "edu.berkeley.cs",
-  version := "1.0",
+  version := "1.3",
  scalaVersion := "2.12.10",
-  traceLevel := 15,
  test in assembly := {},
  assemblyMergeStrategy in assembly := { _ match {
    case PathList("META-INF", "MANIFEST.MF") => MergeStrategy.discard
    case _ => MergeStrategy.first}},
  scalacOptions ++= Seq("-deprecation","-unchecked","-Xsource:2.11"),
-  libraryDependencies += "org.scalatest" %% "scalatest" % "3.0.8" % "test",
-  libraryDependencies += "org.json4s" %% "json4s-jackson" % "3.6.1",
-  libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
-  libraryDependencies += "com.github.scopt" %% "scopt" % "3.7.0",
-  libraryDependencies += "org.scala-lang.modules" % "scala-jline" % "2.12.1",
-  libraryDependencies += "com.typesafe.play" %% "play-json" % "2.6.10",
-  libraryDependencies += "org.typelevel" %% "spire" % "0.16.2",
-  libraryDependencies += "org.scalanlp" %% "breeze" % "1.0",
-  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
+  addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.1" cross CrossVersion.full),
  unmanagedBase := (chipyardRoot / unmanagedBase).value,
-  allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"),
+  allDependencies := {
+    // drop specific maven dependencies in subprojects in favor of Chipyard's version
+    val dropDeps = Seq(
+      ("edu.berkeley.cs", "firrtl"),
+      ("edu.berkeley.cs", "chisel3"),
+      ("edu.berkeley.cs", "rocketchip"),
+      ("edu.berkeley.cs", "chisel-iotesters"),
+      ("edu.berkeley.cs", "treadle"),
+      ("edu.berkeley.cs", "firrtl-interpreter"))
+
+    allDependencies.value.filterNot { dep =>
+      dropDeps.contains((dep.organization, dep.name))
+    }
+  },
  exportJars := true,
  resolvers ++= Seq(
    Resolver.sonatypeRepo("snapshots"),
@@ -40,19 +44,6 @@ lazy val firesimDir = if (firesimAsLibrary) {
  file("../../sim")
 }

-// Checks for -DROCKET_USE_MAVEN.
-// If it's there, use a maven dependency.
-// Else, depend on subprojects in git submodules.
-def conditionalDependsOn(prj: Project): Project = {
-  if (sys.props.contains("ROCKET_USE_MAVEN")) {
-    prj.settings(Seq(
-      libraryDependencies += "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT",
-    ))
-  } else {
-    prj.dependsOn(testchipip)
-  }
-}
-
 /**
  * It has been a struggle for us to override settings in subprojects.
  * An example would be adding a dependency to rocketchip on midas's targetutils library,
@@ -72,149 +63,248 @@ def freshProject(name: String, dir: File): Project = {
 // Fork each scala test for now, to work around persistent mutable state
 // in Rocket-Chip based generators
 def isolateAllTests(tests: Seq[TestDefinition]) = tests map { test =>
-      val options = ForkOptions()
-      new Group(test.name, Seq(test), SubProcess(options))
-  } toSeq
+  val options = ForkOptions()
+  new Group(test.name, Seq(test), SubProcess(options))
+} toSeq

 // Subproject definitions begin
-//
-// FIRRTL is handled as an unmanaged dependency. Make will build the firrtl jar
-// before launching sbt if any of the firrtl source files has been updated
-// The jar is dropped in chipyard's lib/ directory, which is used as the unmanagedBase
-// for all subprojects
-lazy val chisel  = (project in file("tools/chisel3"))
+
+// -- Rocket Chip --
+
+// This needs to stay in sync with the chisel3 and firrtl git submodules
+val chiselVersion = "3.4.0"
+lazy val chiselRef = ProjectRef(workspaceDirectory / "chisel3", "chisel")
+lazy val chiselLib = "edu.berkeley.cs" %% "chisel3" % chiselVersion
+lazy val chiselLibDeps = (chiselRef / Keys.libraryDependencies)
+// While not built from source, *must* be in sync with the chisel3 git submodule
+// Building from source requires extending sbt-sriracha or a similar plugin and
+//   keeping scalaVersion in sync with chisel3 to the minor version
+lazy val chiselPluginLib = "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full
+
+val firrtlVersion = "1.4.+"
+lazy val firrtlRef = ProjectRef(workspaceDirectory / "firrtl", "firrtl")
+lazy val firrtlLib = "edu.berkeley.cs" %% "firrtl" % firrtlVersion
+val firrtlLibDeps = settingKey[Seq[sbt.librarymanagement.ModuleID]]("FIRRTL Library Dependencies sans antlr4")
+Global / firrtlLibDeps := {
+  // drop antlr4 compile dep. but keep antlr4-runtime dep. (compile needs the plugin to be setup)
+  (firrtlRef / Keys.libraryDependencies).value.filterNot(_.name == "antlr4")
+}
+
+ // Rocket-chip dependencies (subsumes making RC a RootProject)
+lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(midasTargetUtils)
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+
+lazy val rocketMacros  = (project in rocketChipDir / "macros")
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+
+lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+
+lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(hardfloat, rocketMacros, rocketConfig)
+  .settings(commonSettings)
+  .settings(
+    libraryDependencies ++= Seq(
+      "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+      "org.json4s" %% "json4s-jackson" % "3.6.1",
+      "org.scalatest" %% "scalatest" % "3.2.0" % "test"
+    )
+  )
+  .settings( // Settings for scalafix
+    semanticdbEnabled := true,
+    semanticdbVersion := scalafixSemanticdb.revision,
+    scalacOptions += "-Ywarn-unused-import"
+  )
+lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
+
+// -- Chipyard-managed External Projects --

 lazy val firrtl_interpreter = (project in file("tools/firrtl-interpreter"))
+  .sourceDependency(firrtlRef, firrtlLib)
  .settings(commonSettings)
+  .settings(libraryDependencies ++= (Global / firrtlLibDeps).value)
+lazy val firrtlInterpreterLibDeps = (firrtl_interpreter / Keys.libraryDependencies)

 lazy val treadle = (project in file("tools/treadle"))
+  .sourceDependency(firrtlRef, firrtlLib)
  .settings(commonSettings)
+  .settings(libraryDependencies ++= (Global / firrtlLibDeps).value)
+lazy val treadleLibDeps = (treadle / Keys.libraryDependencies)

 lazy val chisel_testers = (project in file("tools/chisel-testers"))
-  .dependsOn(chisel, firrtl_interpreter, treadle)
-  .settings(
-      commonSettings,
-      libraryDependencies ++= Seq(
-        "junit" % "junit" % "4.12",
-        "org.scalatest" %% "scalatest" % "3.0.5",
-        "org.scalacheck" %% "scalacheck" % "1.14.0",
-        "com.github.scopt" %% "scopt" % "3.7.0"
-      )
-    )
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(firrtl_interpreter, treadle)
+  .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value)
+  .settings(libraryDependencies ++= treadleLibDeps.value)
+  .settings(commonSettings)
+lazy val chiselTestersLibDeps = (chisel_testers / Keys.libraryDependencies)
+
+// -- Normal Projects --

 // Contains annotations & firrtl passes you may wish to use in rocket-chip without
 // introducing a circular dependency between RC and MIDAS
 lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")

- // Rocket-chip dependencies (subsumes making RC a RootProject)
-lazy val hardfloat  = (project in rocketChipDir / "hardfloat")
-  .settings(commonSettings).dependsOn(midasTargetUtils)
-
-lazy val rocketMacros  = (project in rocketChipDir / "macros")
-  .settings(commonSettings)
-
-lazy val rocketConfig = (project in rocketChipDir / "api-config-chipsalliance/build-rules/sbt")
-  .settings(commonSettings)
-
-lazy val rocketchip = freshProject("rocketchip", rocketChipDir)
-  .settings(commonSettings)
-  .dependsOn(chisel, hardfloat, rocketMacros, rocketConfig)
-
 lazy val testchipip = (project in file("generators/testchipip"))
  .dependsOn(rocketchip, sifive_blocks)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)
+lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHOT"

-lazy val iocell = (project in file("./tools/barstools/iocell/"))
-  .dependsOn(chisel)
-  .settings(commonSettings)
-
-lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
-  .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
+lazy val chipyard = (project in file("generators/chipyard"))
+  .sourceDependency(testchipip, testchipipLib)
+  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
    sha3, // On separate line to allow for cleaner tutorial-setup patches
    dsptools, `rocket-dsptools`,
    gemmini, icenet, tracegen, cva6, nvdla, sodor)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
+lazy val tracegen = (project in file("generators/tracegen"))
+  .sourceDependency(testchipip, testchipipLib)
  .dependsOn(rocketchip, sifive_cache, boom, utilities)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
+lazy val utilities = (project in file("generators/utilities"))
+  .sourceDependency(testchipip, testchipipLib)
  .settings(commonSettings)

 lazy val icenet = (project in file("generators/icenet"))
-  .dependsOn(rocketchip, testchipip)
+  .sourceDependency(testchipip, testchipipLib)
+  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

 lazy val hwacha = (project in file("generators/hwacha"))
  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val boom = conditionalDependsOn(project in file("generators/boom"))
+lazy val boom = (project in file("generators/boom"))
+  .sourceDependency(testchipip, testchipipLib)
  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

 lazy val cva6 = (project in file("generators/cva6"))
  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

 lazy val sodor = (project in file("generators/riscv-sodor"))
  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

 lazy val sha3 = (project in file("generators/sha3"))
  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
  .settings(commonSettings)

 lazy val gemmini = (project in file("generators/gemmini"))
-  .dependsOn(rocketchip, chisel_testers, testchipip)
+  .sourceDependency(testchipip, testchipipLib)
+  .dependsOn(rocketchip, chisel_testers)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
  .settings(commonSettings)

 lazy val nvdla = (project in file("generators/nvdla"))
  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val tapeout = conditionalDependsOn(project in file("./tools/barstools/tapeout/"))
-  .dependsOn(chisel_testers, chipyard)
+lazy val iocell = (project in file("./tools/barstools/iocell/"))
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .settings(commonSettings)
+
+lazy val tapeout = (project in file("./tools/barstools/tapeout/"))
+  .dependsOn(chisel_testers, chipyard) // must depend on chipyard to get scala resources
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
  .settings(commonSettings)
-  .settings(libraryDependencies ++= Seq("io.github.daviddenton" %% "handlebars-scala-fork" % "2.3.0"))

 lazy val mdf = (project in file("./tools/barstools/mdf/scalalib/"))
  .settings(commonSettings)

 lazy val barstoolsMacros = (project in file("./tools/barstools/macros/"))
-  .dependsOn(firrtl_interpreter, mdf, rocketchip)
+  .sourceDependency(chiselRef, chiselLib)
+  .settings(addCompilerPlugin(chiselPluginLib))
+  .settings(libraryDependencies ++= chiselLibDeps.value)
+  .dependsOn(firrtl_interpreter, mdf, chisel_testers)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
+  .settings(libraryDependencies ++= firrtlInterpreterLibDeps.value)
  .enablePlugins(sbtassembly.AssemblyPlugin)
  .settings(commonSettings)

 lazy val dsptools = freshProject("dsptools", file("./tools/dsptools"))
-  .dependsOn(chisel, chisel_testers)
+  .dependsOn(chisel_testers)
+  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
  .settings(
-      commonSettings,
-      libraryDependencies ++= Seq(
-        "junit" % "junit" % "4.13" % "test",
-        "org.scalatest" %% "scalatest" % "3.0.8",
-        "org.scalacheck" %% "scalacheck" % "1.14.3" % "test"
+    commonSettings,
+    libraryDependencies ++= Seq(
+      "org.typelevel" %% "spire" % "0.16.2",
+      "org.scalanlp" %% "breeze" % "1.1",
+      "junit" % "junit" % "4.13" % "test",
+      "org.scalatest" %% "scalatest" % "3.0.+" % "test",
+      "org.scalacheck" %% "scalacheck" % "1.14.3" % "test",
  ))

 lazy val `rocket-dsptools` = freshProject("rocket-dsptools", file("./tools/dsptools/rocket"))
  .dependsOn(rocketchip, dsptools)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

 lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

-lazy val sifive_cache = (project in file("generators/sifive-cache")).settings(
+lazy val sifive_cache = (project in file("generators/sifive-cache"))
+  .settings(
    commonSettings,
-    scalaSource in Compile := baseDirectory.value / "design/craft"
-  ).dependsOn(rocketchip)
+    scalaSource in Compile := baseDirectory.value / "design/craft")
+  .dependsOn(rocketchip)
+  .settings(libraryDependencies ++= rocketLibDeps.value)

 // Library components of FireSim
 lazy val midas      = ProjectRef(firesimDir, "midas")
 lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")

-lazy val firechip = conditionalDependsOn(project in file("generators/firechip"))
+lazy val firechip = (project in file("generators/firechip"))
+  .sourceDependency(testchipip, testchipipLib)
  .dependsOn(chipyard, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
  .settings(
    commonSettings,
--- a/common.mk
+++ b/common.mk
@@ -17,7 +17,8 @@ HELP_COMPILATION_VARIABLES += \
 "   EXTRA_SIM_CXXFLAGS     = additional CXXFLAGS for building simulators" \
 "   EXTRA_SIM_LDFLAGS      = additional LDFLAGS for building simulators" \
 "   EXTRA_SIM_SOURCES      = additional simulation sources needed for simulator" \
-"   EXTRA_SIM_REQS         = additional make requirements to build the simulator"
+"   EXTRA_SIM_REQS         = additional make requirements to build the simulator" \
+"   ENABLE_SBT_THIN_CLIENT = if set, use sbt's experimental thin client"

 EXTRA_GENERATOR_REQS ?=
 EXTRA_SIM_CXXFLAGS   ?=
@@ -41,7 +42,9 @@ HELP_COMMANDS += \
 "   run-binary-fast        = run [./$(shell basename $(sim))] and don't log instructions" \
 "   run-binary-debug       = run [./$(shell basename $(sim_debug))] and log instructions and waveform to files" \
 "   verilog                = generate intermediate verilog files from chisel elaboration and firrtl passes" \
-"   run-tests              = run all assembly and benchmark tests"
+"   firrtl                 = generate intermediate firrtl files from chisel elaboration" \
+"   run-tests              = run all assembly and benchmark tests" \
+"   launch-sbt             = start sbt terminal"

 #########################################################################################
 # include additional subproject make fragments
@@ -63,37 +66,23 @@ SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
 VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
 # This assumes no SBT meta-build sources
 SBT_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools)
-SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt
+SBT_SOURCES = $(call lookup_srcs,$(SBT_SOURCE_DIRS),sbt) $(base_dir)/build.sbt $(base_dir)/project/plugins.sbt $(base_dir)/project/build.properties

 #########################################################################################
-# jar creation variables and rules
+# SBT Server Setup (start server / rebuild proj. defs. if SBT_SOURCES change)
 #########################################################################################
-FIRRTL_JAR := $(base_dir)/lib/firrtl.jar
-FIRRTL_TEST_JAR := $(base_dir)/test_lib/firrtl-test.jar
-
-$(FIRRTL_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
-	$(MAKE) -C $(CHIPYARD_FIRRTL_DIR) SBT="$(SBT)" root_dir=$(CHIPYARD_FIRRTL_DIR) build-scala
-	mkdir -p $(@D)
-	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl.jar $@
-	touch $@
-
-$(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
-	cd $(CHIPYARD_FIRRTL_DIR) && $(SBT) "test:assembly"
-	mkdir -p $(@D)
-	cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
-	touch $@
-
-#########################################################################################
-# Bloop Project Definitions
-#########################################################################################
-$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES)
-	cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall"
+$(SBT_THIN_CLIENT_TIMESTAMP): $(SBT_SOURCES)
+ifneq (,$(wildcard $(SBT_THIN_CLIENT_TIMESTAMP)))
+	cd $(base_dir) && $(SBT) "reload"
 	touch $@
+else
+	cd $(base_dir) && $(SBT) "exit"
+endif

 #########################################################################################
 # create list of simulation file inputs
 #########################################################################################
-$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS)
+$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(SCALA_BUILDTOOL_DEPS)
 	$(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name))

 #########################################################################################
@@ -227,7 +216,7 @@ ifneq ($(filter run% %.run %.out %.vpd %.vcd,$(MAKECMDGOALS)),)
 endif

 #######################################
-# Rules for building DRAMSim2 library #
+# Rules for building DRAMSim2 library
 #######################################

 dramsim_dir = $(base_dir)/tools/DRAMSim2
@@ -236,6 +225,23 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a
 $(dramsim_lib):
 	$(MAKE) -C $(dramsim_dir) $(notdir $@)

+################################################
+# Helper to run SBT or manage the SBT server
+################################################
+
+SBT_COMMAND ?= shell
+.PHONY: launch-sbt
+launch-sbt:
+	cd $(base_dir) && $(SBT_NON_THIN) "$(SBT_COMMAND)"
+
+.PHONY: shutdown-sbt-server
+shutdown-sbt-server:
+	cd $(base_dir) && $(SBT) "shutdown"
+
+.PHONY: start-sbt-server
+start-sbt-server:
+	cd $(base_dir) && $(SBT) "exit"
+
 #########################################################################################
 # print help text
 #########################################################################################
--- a/generators/boom
+++ b/generators/boom
--- a/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala
+++ b/generators/chipyard/src/main/scala/clocking/ResetSynchronizer.scala
@@ -1,30 +0,0 @@
-
-package chipyard.clocking
-
-import chisel3._
-
-import freechips.rocketchip.config.{Parameters}
-import freechips.rocketchip.diplomacy._
-import freechips.rocketchip.prci._
-import freechips.rocketchip.util.{ResetCatchAndSync}
-
-/**
-  * Instantiates a reset synchronizer on all clock-reset pairs in a clock group
-  */
-class ClockGroupResetSynchronizer(implicit p: Parameters) extends LazyModule {
-  val node = ClockGroupAdapterNode()
-  lazy val module = new LazyRawModuleImp(this) {
-    (node.out zip node.in).map { case ((oG, _), (iG, _)) =>
-      (oG.member.data zip iG.member.data).foreach { case (o, i) =>
-        o.clock := i.clock
-        o.reset := ResetCatchAndSync(i.clock, i.reset.asBool)
-      }
-    }
-  }
-}
-
-object ClockGroupResetSynchronizer {
-  def apply()(implicit p: Parameters, valName: ValName) = LazyModule(new ClockGroupResetSynchronizer()).node
-}
-
-
--- a/generators/chipyard/src/main/scala/example/NodeTypes.scala
+++ b/generators/chipyard/src/main/scala/example/NodeTypes.scala
@@ -11,7 +11,7 @@ import testchipip.TLHelper

 // DOC include start: MyClient
 class MyClient(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeClientNode(TLClientParameters(
+  val node = TLHelper.makeClientNode(TLMasterParameters.v1(
    name = "my-client",
    sourceId = IdRange(0, 4),
    requestFifo = true,
@@ -29,7 +29,7 @@ class MyClient(implicit p: Parameters) extends LazyModule {
 class MyManager(implicit p: Parameters) extends LazyModule {
  val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
  val beatBytes = 8
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
    address = Seq(AddressSet(0x20000, 0xfff)),
    resources = device.reg,
    regionType = RegionType.UNCACHED,
@@ -83,7 +83,7 @@ class MyClientGroup(implicit p: Parameters) extends LazyModule {

 // DOC include start: MyManagerGroup
 class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
    address = Seq(AddressSet(0x0, 0xfff))))

  lazy val module = new LazyModuleImp(this) {
@@ -92,7 +92,7 @@ class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
 }

 class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
-  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+  val node = TLHelper.makeManagerNode(beatBytes, TLSlaveParameters.v1(
    address = Seq(AddressSet(0x1000, 0xfff))))

  lazy val module = new LazyModuleImp(this) {
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -43,6 +43,8 @@ case class MyCoreParams(
  val pmpGranularity: Int = 4 // copied from Rocket
  val nBreakpoints: Int = 0 // TODO: Check
  val useBPWatch: Boolean = false
+  val mcontextWidth: Int = 0
+  val scontextWidth: Int = 0
  val nPerfCounters: Int = 29
  val haveBasicCounters: Boolean = true
  val haveFSDirty: Boolean = false
--- a/generators/cva6
+++ b/generators/cva6
--- a/generators/firechip/src/main/scala/BridgeBinders.scala
+++ b/generators/firechip/src/main/scala/BridgeBinders.scala
@@ -4,12 +4,13 @@ package firesim.firesim

 import chisel3._
 import chisel3.experimental.annotate
+import chisel3.util.experimental.BoringUtils

 import freechips.rocketchip.config.{Field, Config, Parameters}
 import freechips.rocketchip.diplomacy.{LazyModule}
 import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle}
-import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp, ExtMem}
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile.{RocketTile}
 import sifive.blocks.devices.uart._

@@ -86,7 +87,12 @@ class WithNICBridge extends OverrideHarnessBinder({

 class WithUARTBridge extends OverrideHarnessBinder({
  (system: HasPeripheryUARTModuleImp, th: FireSim, ports: Seq[UARTPortIO]) =>
-    ports.map { p => UARTBridge(th.harnessClock, p)(system.p) }; Nil
+    val uartSyncClock = Wire(Clock())
+    uartSyncClock := false.B.asClock
+    val pbusClockNode = system.outer.asInstanceOf[HasTileLinkLocations].locateTLBusWrapper(PBUS).fixedClockNode
+    val pbusClock = pbusClockNode.in.head._1.clock
+    BoringUtils.bore(pbusClock, Seq(uartSyncClock))
+    ports.map { p => UARTBridge(uartSyncClock, p)(system.p) }; Nil
 })

 class WithBlockDeviceBridge extends OverrideHarnessBinder({
--- a/generators/firechip/src/test/scala/ScalaTestSuite.scala
+++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala
@@ -42,10 +42,9 @@ abstract class FireSimTestSuite(
  }

  def runTest(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
-    behavior of s"${name} running on ${backend} in MIDAS-level simulation"
    compileMlSimulator(backend, debug)
    if (isCmdAvailable(backend)) {
-      it should s"pass" in {
+      it should s"pass in ML simulation on ${backend}" in {
        assert(invokeMlSimulator(backend, name, debug, additionalArgs) == 0)
      }
    }
@@ -59,13 +58,15 @@ abstract class FireSimTestSuite(
        case _: BenchmarkTestSuite | _: BlockdevTestSuite | _: NICTestSuite => ".riscv"
        case _ => ""
      }
-      val results = suite.names.toSeq sliding (N, N) map { t =>
-        val subresults = t map (name =>
-          Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
-        Await result (Future sequence subresults, Duration.Inf)
-      }
-      results.flatten foreach { case (name, exitcode) =>
-        it should s"pass $name" in { assert(exitcode == 0) }
+      it should s"pass all tests in ${suite.makeTargetName}" in {
+        val results = suite.names.toSeq sliding (N, N) map { t =>
+          val subresults = t map (name =>
+            Future(name -> invokeMlSimulator(backend, s"$name$postfix", debug)))
+          Await result (Future sequence subresults, Duration.Inf)
+        }
+        results.flatten foreach { case (name, exitcode) =>
+          assert(exitcode == 0, "Failed $name")
+        }
      }
    } else {
      ignore should s"pass $backend"
@@ -96,7 +97,9 @@ abstract class FireSimTestSuite(
    }
  }

-  clean
+  mkdirs
+  behavior of s"Tuple: ${targetTuple}"
+  elaborateAndCompile()
  runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-humanreadable0"""))
  runSuite("verilator")(benchmarks)
 }
--- a/generators/gemmini
+++ b/generators/gemmini
--- a/generators/hwacha
+++ b/generators/hwacha
--- a/generators/icenet
+++ b/generators/icenet
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
--- a/generators/sha3
+++ b/generators/sha3
--- a/generators/sifive-blocks
+++ b/generators/sifive-blocks
--- a/generators/sifive-cache
+++ b/generators/sifive-cache
--- a/generators/testchipip
+++ b/generators/testchipip
--- a/project/build.properties
+++ b/project/build.properties
@@ -1 +1 @@
-sbt.version=1.3.2
+sbt.version=1.4.4
--- a/project/plugins.sbt
+++ b/project/plugins.sbt
@@ -1,20 +1,15 @@
-resolvers += Resolver.url("scalasbt", new URL("https://scalasbt.artifactoryonline.com/scalasbt/sbt-plugin-releases")) (Resolver.ivyStylePatterns)
-resolvers += Classpaths.sbtPluginReleases
-resolvers += "jgit-repo" at "https://download.eclipse.org/jgit/maven"
-
 addSbtPlugin("net.virtual-void" % "sbt-dependency-graph" % "0.9.2")
 addSbtPlugin("com.typesafe.sbt" % "sbt-ghpages" % "0.6.2")
 addSbtPlugin("com.typesafe.sbt" % "sbt-site" % "1.3.1")
-addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.7.0")
+addSbtPlugin("com.eed3si9n" % "sbt-buildinfo" % "0.10.0")
 addSbtPlugin("org.xerial.sbt" % "sbt-pack" % "0.9.3")
 addSbtPlugin("com.eed3si9n" % "sbt-unidoc" % "0.4.1")
 addSbtPlugin("org.scoverage" % "sbt-scoverage" % "1.5.1")
 addSbtPlugin("org.scalastyle" %% "scalastyle-sbt-plugin" % "1.0.0")
-addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.6")
-addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.15.0")
+addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.2")
 addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3")
-addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4")
+addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.21")
 addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1")
-addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1")
-
-libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1"
+addSbtPlugin("com.eed3si9n" % "sbt-sriracha" % "0.1.0")
+addSbtPlugin("org.scalameta" % "sbt-mdoc" % "2.2.5" )
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -1,26 +1,30 @@
 diff --git a/build.sbt b/build.sbt
-index 5d642c1..56f6fda 100644
+index e80b2a5..b1989d9 100644
 --- a/build.sbt
 +++ b/build.sbt
-@@ -130,7 +130,7 @@ lazy val iocell = (project in file("./tools/barstools/iocell/"))
-
- lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
-   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
+@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO
+ lazy val chipyard = (project in file("generators/chipyard"))
+   .sourceDependency(testchipip, testchipipLib)
+   .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsptools`,
     gemmini, icenet, tracegen, cva6, nvdla, sodor)
+   .settings(libraryDependencies ++= rocketLibDeps.value)
+@@ -227,11 +227,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
+   .settings(libraryDependencies ++= rocketLibDeps.value)
   .settings(commonSettings)
-@@ -158,9 +158,9 @@ lazy val cva6 = (project in file("generators/cva6"))
-   .dependsOn(rocketchip)
-   .settings(commonSettings)
-
+ 
 -lazy val sha3 = (project in file("generators/sha3"))
 -  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+-  .settings(libraryDependencies ++= rocketLibDeps.value)
+-  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
 -  .settings(commonSettings)
 +//lazy val sha3 = (project in file("generators/sha3"))
 +//  .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
+//  .settings(libraryDependencies ++= rocketLibDeps.value)
+//  .settings(libraryDependencies ++= chiselTestersLibDeps.value)
 +//  .settings(commonSettings)
-
+ 
 lazy val gemmini = (project in file("generators/gemmini"))
-   .dependsOn(rocketchip, chisel_testers, testchipip)
+   .sourceDependency(testchipip, testchipipLib)
--- a/sims/firesim
+++ b/sims/firesim
--- a/tools/barstools
+++ b/tools/barstools
--- a/tools/chisel-testers
+++ b/tools/chisel-testers
--- a/tools/chisel3
+++ b/tools/chisel3
--- a/tools/dsptools
+++ b/tools/dsptools
--- a/tools/firrtl
+++ b/tools/firrtl
--- a/tools/firrtl-interpreter
+++ b/tools/firrtl-interpreter
--- a/tools/treadle
+++ b/tools/treadle
--- a/variables.mk
+++ b/variables.mk
@@ -146,40 +146,31 @@ sim_common_files       ?= $(build_dir)/sim_files.common.f
 # java arguments used in sbt
 #########################################################################################
 JAVA_HEAP_SIZE ?= 8G
-JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M
+JAVA_OPTS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M

 #########################################################################################
 # default sbt launch command
 #########################################################################################
-SCALA_VERSION=2.12.10
-SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
-SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar
-
-BLOOP ?= bloop
-BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop
-# This mirrors the bloop default. Set to a system-unique port in a multi-user environment
-BLOOP_NAILGUN_PORT ?= 8212
+# by default build chisel3/firrtl and other subprojects from source
+override SBT_OPTS += -Dsbt.sourcemode=true -Dsbt.workspace=$(base_dir)/tools

 SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)

-ifdef ENABLE_BLOOP
-override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP
-# Two notes about the bloop invocation:
-# 1) the sed removes a leading {file:<path>} that sometimes needs to be
-#    provided to SBT when a project but not for bloop.
-# 2) Generally, one could could pass '--' to indicate all remaining arguments are
-#    destined for the scala Main, however a bug in Bloop's argument parsing causes the
-#    --nailgun-port argument to be lost in this case. Workaround this by prefixing
-#    every main-destined argument with "--args"
-define run_scala_main
-	cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2)  $(addprefix --args ,$3)
-endef
-else
-define run_scala_main
-	cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)"
-endef
+SBT_THIN_CLIENT_TIMESTAMP = $(base_dir)/project/target/active.json
+
+ifdef ENABLE_SBT_THIN_CLIENT
+override SCALA_BUILDTOOL_DEPS += $(SBT_THIN_CLIENT_TIMESTAMP)
+# enabling speeds up sbt loading
+SBT_CLIENT_FLAG = --client
 endif

+SBT ?= java $(JAVA_OPTS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar $(SBT_OPTS) $(SBT_CLIENT_FLAG)
+SBT_NON_THIN ?= $(subst $(SBT_CLIENT_FLAG),,$(SBT))
+
+define run_scala_main
+	cd $(base_dir) && $(SBT) ";project $(1); runMain $(2) $(3)"
+endef
+
 FIRRTL_LOGLEVEL ?= error

 #########################################################################################