Add coherent chiplet config

generators/chipyard/src/main/scala/config/ChipletConfigs.scala

@@ -45,3 +45,49 @@ class MultiSimSymmetricChipletRocketConfig extends Config(
   new chipyard.harness.WithMultiChip(0, new SymmetricChipletRocketConfig) ++
   new chipyard.harness.WithMultiChip(1, new SymmetricChipletRocketConfig)
 )
+
+// Core-only chiplet config, where the coherent memory is located on the LLC-chiplet
+class RocketCoreChipletConfig extends Config(
+  new testchipip.serdes.WithSerialTL(Seq(
+    testchipip.serdes.SerialTLParams(
+      client = Some(testchipip.serdes.SerialTLClientParams()),
+      phyParams = testchipip.serdes.ExternalSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+    ),
+    testchipip.serdes.SerialTLParams(
+      manager = Some(testchipip.serdes.SerialTLManagerParams(
+        cohParams = Seq(testchipip.serdes.ManagerCOHParams(
+          address = BigInt("80000000", 16),
+          size    = BigInt("100000000", 16)
+        )),
+        slaveWhere = OBUS,
+        isMemoryDevice = true
+      )),
+      phyParams = testchipip.serdes.SourceSyncSerialPhyParams()
+    )
+  )) ++
+  new testchipip.soc.WithOffchipBusClient(SBUS) ++
+  new testchipip.soc.WithOffchipBus ++
+  new testchipip.soc.WithNoScratchpads ++
+  new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++
+  new freechips.rocketchip.subsystem.WithNoMemPort ++
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new chipyard.config.AbstractConfig)
+
+// LLC-only chiplet
+class LLCChipletConfig extends Config(
+  new chipyard.harness.WithSerialTLTiedOff ++
+  new testchipip.serdes.WithSerialTL(Seq(testchipip.serdes.SerialTLParams(                               // 1st serial-tl is chip-to-chip
+    client = Some(testchipip.serdes.SerialTLClientParams(supportsProbe=true)),
+    phyParams = testchipip.serdes.SourceSyncSerialPhyParams()     // chip-to-chip serial-tl is symmetric source-sync'd
+  ))) ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++
+  new chipyard.NoCoresConfig
+)
+
+class MultiSimLLCChipletRocketConfig extends Config(
+  new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++
+  new chipyard.harness.WithMultiChipSerialTL(chip0=0, chip1=1, chip0portId=1, chip1portId=0) ++
+  new chipyard.harness.WithMultiChip(0, new RocketCoreChipletConfig) ++
+  new chipyard.harness.WithMultiChip(1, new LLCChipletConfig)
+)

generators/chipyard/src/main/scala/harness/HarnessBinders.scala

@@ -219,6 +219,7 @@ class WithSerialTLTiedOff(tieoffs: Option[Seq[Int]] = None) extends HarnessBinde
     port.io match {
       case io: InternalSyncPhitIO =>
       case io: ExternalSyncPhitIO => io.clock_in := false.B.asClock
+      case io: SourceSyncPhitIO =>
       case _ =>
     }
   }
@@ -229,6 +230,7 @@ class WithSimTSIOverSerialTL extends HarnessBinder({
     port.io match {
       case io: InternalSyncPhitIO =>
       case io: ExternalSyncPhitIO => io.clock_in := th.harnessBinderClock
+      case io: SourceSyncPhitIO => io.clock_in := th.harnessBinderClock; io.reset_in := th.harnessBinderReset
     }
 
     port.io match {