Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework

2019-09-19 09:42:09 -07:00
parent c461540f65 a77226cdba
commit 6bb1de5a59
77 changed files with 3395 additions and 909 deletions
--- a/generators/firechip/src/main/scala/Generator.scala
+++ b/generators/firechip/src/main/scala/Generator.scala
@@ -16,80 +16,14 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.subsystem.RocketTilesKey
 import freechips.rocketchip.tile.XLen

-import boom.system.{BoomTilesKey, BoomTestSuites}
-
 import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}

+import utilities.TestSuiteHelper
+
 trait HasTestSuites {
-  val rv64RegrTestNames = collection.mutable.LinkedHashSet(
-      "rv64ud-v-fcvt",
-      "rv64ud-p-fdiv",
-      "rv64ud-v-fadd",
-      "rv64uf-v-fadd",
-      "rv64um-v-mul",
-      // "rv64mi-p-breakpoint", // Not implemented in BOOM
-      // "rv64uc-v-rvc", // Not implemented in BOOM
-      "rv64ud-v-structural",
-      "rv64si-p-wfi",
-      "rv64um-v-divw",
-      "rv64ua-v-lrsc",
-      "rv64ui-v-fence_i",
-      "rv64ud-v-fcvt_w",
-      "rv64uf-v-fmin",
-      "rv64ui-v-sb",
-      "rv64ua-v-amomax_d",
-      "rv64ud-v-move",
-      "rv64ud-v-fclass",
-      "rv64ua-v-amoand_d",
-      "rv64ua-v-amoxor_d",
-      "rv64si-p-sbreak",
-      "rv64ud-v-fmadd",
-      "rv64uf-v-ldst",
-      "rv64um-v-mulh",
-      "rv64si-p-dirty")
-
-  val rv32RegrTestNames = collection.mutable.LinkedHashSet(
-      "rv32mi-p-ma_addr",
-      "rv32mi-p-csr",
-      "rv32ui-p-sh",
-      "rv32ui-p-lh",
-      "rv32uc-p-rvc",
-      "rv32mi-p-sbreak",
-      "rv32ui-p-sll")
-
  def addTestSuites(targetName: String, params: Parameters) {
-    val coreParams =
-      if (params(RocketTilesKey).nonEmpty) {
-        params(RocketTilesKey).head.core
-      } else {
-        params(BoomTilesKey).head.core
-      }
-    val xlen = params(XLen)
-    val vm = coreParams.useVM
-    val env = if (vm) List("p","v") else List("p")
-    coreParams.fpu foreach { case cfg =>
-      if (xlen == 32) {
-        TestGeneration.addSuites(env.map(rv32uf))
-        if (cfg.fLen >= 64)
-          TestGeneration.addSuites(env.map(rv32ud))
-      } else {
-        TestGeneration.addSuite(rv32udBenchmarks)
-        TestGeneration.addSuites(env.map(rv64uf))
-        if (cfg.fLen >= 64)
-          TestGeneration.addSuites(env.map(rv64ud))
-      }
-    }
-    if (coreParams.useAtomics)    TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-    if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-    val (rvi, rvu) =
-      if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
-      else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-      else            ((if (vm) rv32i else rv32pi), rv32u)
-
-    TestGeneration.addSuites(rvi.map(_("p")))
-    TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-    TestGeneration.addSuite(benchmarks)
-    TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    TestSuiteHelper.addRocketTestSuites(params)
+    TestSuiteHelper.addBoomTestSuites(params)
    TestGeneration.addSuite(FastBlockdevTests)
    TestGeneration.addSuite(SlowBlockdevTests)
    if (!targetName.contains("NoNIC"))
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -4,14 +4,18 @@ import java.io.File

 import chisel3.util.{log2Up}
 import freechips.rocketchip.config.{Parameters, Config}
+import freechips.rocketchip.groundtest.TraceGenParams
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.DebugModuleParams
-import boom.system.BoomTilesKey
+import boom.common.BoomTilesKey
 import testchipip.{BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
+import scala.math.{min, max}
+import tracegen.TraceGenKey
 import icenet._

 import firesim.endpoints._
@@ -143,8 +147,10 @@ class FireSimBoomConfig extends Config(
  new WithBoomL2TLBs(1024) ++
  new WithoutClockGating ++
  new WithDefaultMemModel ++
-  // Using a small config because it has 64-bit system bus, and compiles quickly
-  new boom.system.SmallBoomConfig)
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig
+)

 // A safer implementation than the one in BOOM in that it
 // duplicates whatever BOOMTileKey.head is present N times. This prevents
@@ -210,3 +216,69 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
  new WithExtMemSize(0x200000000L) ++ // 8GB
  new FireSimRocketChipOctaCoreConfig)

+class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+    extends Config((site, here, up) => {
+  case TraceGenKey => params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val nSets = dcp.nSets
+      val nWays = dcp.nWays
+      val blockOffset = site(SystemBusKey).blockOffset
+      val nBeats = min(2, site(SystemBusKey).blockBeats)
+      val beatBytes = site(SystemBusKey).beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => log2Up(params.size)
+})
+
+class FireSimTraceGenConfig extends Config(
+  new WithTraceGen(
+    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new FireSimRocketChipConfig)
+
+class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+    extends Config((site, here, up) => {
+  case TraceGenKey => params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val sbp = site(SystemBusKey)
+      val l2p = site(InclusiveCacheKey)
+      val nSets = max(l2p.sets, dcp.nSets)
+      val nWays = max(l2p.ways, dcp.nWays)
+      val nBanks = site(BankedL2Key).nBanks
+      val blockOffset = sbp.blockOffset
+      val nBeats = min(2, sbp.blockBeats)
+      val beatBytes = sbp.beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => log2Up(params.size)
+})
+
+class FireSimTraceGenL2Config extends Config(
+  new WithL2TraceGen(
+    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new WithInclusiveCache(
+    nBanks = 4,
+    capacityKB = 1024,
+    outerLatencyCycles = 50) ++
+  new FireSimRocketChipConfig)
--- a/generators/firechip/src/main/scala/TargetMixins.scala
+++ b/generators/firechip/src/main/scala/TargetMixins.scala
@@ -74,10 +74,10 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
  ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
 }

-trait CanHaveBoomMultiCycleRegfileImp {
-  val outer: boom.system.BoomRocketSubsystem
-  val cores = outer.boomTiles.map(tile => tile.module.core)
-  cores.foreach({ core =>
+trait CanHaveMultiCycleRegfileImp {
+  val outer: utilities.HasBoomAndRocketTiles
+  val boomCores = outer.boomTiles.map(tile => tile.module.core)
+  boomCores.foreach({ core =>
    core.iregfile match {
      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
      case _ => Nil
@@ -87,11 +87,8 @@ trait CanHaveBoomMultiCycleRegfileImp {
      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
      case _ => Nil
    }
+  })

-   })
-}
-trait CanHaveRocketMultiCycleRegfileImp {
-  val outer: RocketSubsystem
  outer.rocketTiles.foreach({ tile =>
    annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
    tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
--- a/generators/firechip/src/main/scala/Targets.scala
+++ b/generators/firechip/src/main/scala/Targets.scala
@@ -12,10 +12,11 @@ import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.amba.axi4.AXI4Bundle
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.LazyModule
-import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp}
+import utilities.{Subsystem, SubsystemModuleImp}
 import icenet._
 import testchipip._
 import testchipip.SerialAdapter.SERIAL_IF_WIDTH
+import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
 import sifive.blocks.devices.uart._
 import java.io.File

@@ -36,8 +37,8 @@ import FireSimValName._
 * determine which driver to build.
 *******************************************************************************/

-class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
-    with HasDefaultBusConfiguration
+class FireSimDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
    with CanHaveMasterAXI4MemPort
    with HasPeripheryBootROM
    with HasPeripherySerial
@@ -49,7 +50,7 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
  override lazy val module = new FireSimModuleImp(this)
 }

-class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l)
+class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
    with HasRTCModuleImp
    with CanHaveMasterAXI4MemPortModuleImp
    with HasPeripheryBootROMModuleImp
@@ -58,12 +59,12 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(
    with HasPeripheryIceNICModuleImpValidOnly
    with HasPeripheryBlockDeviceModuleImp
    with HasTraceIOImp
-    with CanHaveRocketMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp

 class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)

-class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
-    with HasDefaultBusConfiguration
+class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
    with CanHaveMasterAXI4MemPort
    with HasPeripheryBootROM
    with HasPeripherySerial
@@ -74,7 +75,7 @@ class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
  override lazy val module = new FireSimNoNICModuleImp(this)
 }

-class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l)
+class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l)
    with HasRTCModuleImp
    with CanHaveMasterAXI4MemPortModuleImp
    with HasPeripheryBootROMModuleImp
@@ -82,13 +83,13 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem
    with HasPeripheryUARTModuleImp
    with HasPeripheryBlockDeviceModuleImp
    with HasTraceIOImp
-    with CanHaveRocketMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp


 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT)

-class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasDefaultBusConfiguration
+class FireBoomDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
    with CanHaveMasterAXI4MemPort
    with HasPeripheryBootROM
    with HasPeripherySerial
@@ -100,7 +101,7 @@ class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
  override lazy val module = new FireBoomModuleImp(this)
 }

-class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l)
+class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l)
    with HasRTCModuleImp
    with CanHaveMasterAXI4MemPortModuleImp
    with HasPeripheryBootROMModuleImp
@@ -110,12 +111,12 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu
    with HasPeripheryBlockDeviceModuleImp
    with HasTraceIOImp
    with ExcludeInvalidBoomAssertions
-    with CanHaveBoomMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp

 class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT)

-class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasDefaultBusConfiguration
+class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
    with CanHaveMasterAXI4MemPort
    with HasPeripheryBootROM
    with HasPeripherySerial
@@ -126,7 +127,7 @@ class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
  override lazy val module = new FireBoomNoNICModuleImp(this)
 }

-class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l)
+class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModuleImp(l)
    with HasRTCModuleImp
    with CanHaveMasterAXI4MemPortModuleImp
    with HasPeripheryBootROMModuleImp
@@ -135,9 +136,20 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub
    with HasPeripheryBlockDeviceModuleImp
    with HasTraceIOImp
    with ExcludeInvalidBoomAssertions
-    with CanHaveBoomMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp

 class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT)

+class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
+    with HasHierarchicalBusTopology
+    with HasTraceGenTiles
+    with CanHaveMasterAXI4MemPort {
+  override lazy val module = new FireSimTraceGenModuleImp(this)
+}
+
+class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModuleImp(outer)
+    with HasTraceGenTilesModuleImp
+    with CanHaveMasterAXI4MemPortModuleImp
+
 // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1
 class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)