Merge remote-tracking branch 'origin/dev' into midas2-endpoint-rework

generators/example/src/main/scala/BoomConfigs.scala

@@ -3,88 +3,57 @@ package example
 import chisel3._
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithJtagDTM}
-
-import boom.common._
 
 // ---------------------
 // BOOM Configs
 // ---------------------
 
 class SmallBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallBoomConfig)
+  new WithTop ++                                            // use normal top
+  new WithBootROM ++                                        // use testchipip bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++  // use SiFive L2 cache
+  new boom.common.WithSmallBooms ++                         // 1-wide BOOM
+  new boom.common.WithNBoomCores(1) ++                      // single-core
+  new freechips.rocketchip.system.BaseConfig)               // "base" rocketchip system
 
 class MediumBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.MediumBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithMediumBooms ++                        // 2-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class LargeBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.LargeBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithLargeBooms ++                         // 3-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
 class MegaBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.MegaBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithMegaBooms ++                          // 4-wide BOOM
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
 
-class jtagSmallBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
+class DualSmallBoomConfig extends Config(
+  new WithTop ++
   new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.SmallBoomConfig)
-
-class jtagMediumBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
-  new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.MediumBoomConfig)
-
-class jtagLargeBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
-  new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.LargeBoomConfig)
-
-class jtagMegaBoomConfig extends Config(
-  new WithDTMBoomRocketTop ++
-  new WithBootROM ++
-  new WithJtagDTM ++
-  new boom.common.MegaBoomConfig)
-
-class SmallDualBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallDualBoomConfig)
-
-class TracedSmallBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.TracedSmallBoomConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(2) ++                      // dual-core
+  new freechips.rocketchip.system.BaseConfig)
 
 class SmallRV32UnifiedBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
+  new WithTop ++
   new WithBootROM ++
-  new boom.common.SmallRV32UnifiedBoomConfig)
-
-// --------------------------
-// BOOM + Rocket Configs
-// --------------------------
-
-class SmallBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallBoomAndRocketConfig)
-
-class MediumBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.MediumBoomAndRocketConfig)
-
-class DualMediumBoomAndDualRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.DualMediumBoomAndDualRocketConfig)
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithoutBoomFPU ++                       // no floating point
+  new boom.common.WithUnifiedMemIntIQs ++                 // use unified mem+int issue queues
+  new boom.common.WithSmallBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)

generators/example/src/main/scala/ConfigMixins.scala

@@ -9,7 +9,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC}
 
-import boom.system.{BoomTilesKey}
+import boom.common.{BoomTilesKey}
 
 import testchipip._
 
@@ -52,43 +52,45 @@ class WithGPIO extends Config((site, here, up) => {
 /**
  * Class to specify a "plain" top level BOOM and/or Rocket system
  */
-class WithNormalBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    Module(LazyModule(new BoomRocketTop()(p)).module)
+class WithTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    Module(LazyModule(new Top()(p)).module)
   }
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with DTM
  */
-class WithDTMBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
-    Module(LazyModule(new BoomRocketTopWithDTM()(p)).module)
+class WithDTMTop extends Config((site, here, up) => {
+  case BuildTopWithDTM => (clock: Clock, reset: Bool, p: Parameters) => {
+    Module(LazyModule(new TopWithDTM()(p)).module)
   }
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with PWM
  */
-class WithPWMBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
-    Module(LazyModule(new BoomRocketTopWithPWMTL()(p)).module)
+// DOC include start: WithPWMTop
+class WithPWMTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+    Module(LazyModule(new TopWithPWMTL()(p)).module)
 })
+// DOC include end: WithPWMTop
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with a PWM AXI4
  */
-class WithPWMAXI4BoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) =>
-    Module(LazyModule(new BoomRocketTopWithPWMAXI4()(p)).module)
+class WithPWMAXI4Top extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+    Module(LazyModule(new TopWithPWMAXI4()(p)).module)
 })
 
 /**
  * Class to specify a top level BOOM and/or Rocket system with a block device
  */
-class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
+class WithBlockDeviceModelTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
     top.connectBlockDeviceModel()
     top
   }
@@ -97,9 +99,9 @@ class WithBlockDeviceModelBoomRocketTop extends Config((site, here, up) => {
 /**
  * Class to specify a top level BOOM and/or Rocket system with a simulator block device
  */
-class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    val top = Module(LazyModule(new BoomRocketTopWithBlockDevice()(p)).module)
+class WithSimBlockDeviceTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithBlockDevice()(p)).module)
     top.connectSimBlockDevice(clock, reset)
     top
   }
@@ -108,9 +110,9 @@ class WithSimBlockDeviceBoomRocketTop extends Config((site, here, up) => {
 /**
  * Class to specify a top level BOOM and/or Rocket system with GPIO
  */
-class WithGPIOBoomRocketTop extends Config((site, here, up) => {
-  case BuildBoomRocketTop => (clock: Clock, reset: Bool, p: Parameters) => {
-    val top = Module(LazyModule(new BoomRocketTopWithGPIO()(p)).module)
+class WithGPIOTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) => {
+    val top = Module(LazyModule(new TopWithGPIO()(p)).module)
     for (gpio <- top.gpio) {
       for (pin <- gpio.pins) {
         pin.i.ival := false.B
@@ -157,3 +159,14 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
     }
   }
 })
+
+// DOC include start: WithInitZero
+class WithInitZero(base: BigInt, size: BigInt) extends Config((site, here, up) => {
+  case InitZeroKey => InitZeroConfig(base, size)
+})
+
+class WithInitZeroTop extends Config((site, here, up) => {
+  case BuildTop => (clock: Clock, reset: Bool, p: Parameters) =>
+    Module(LazyModule(new TopWithInitZero()(p)).module)
+})
+// DOC include end: WithInitZero

generators/example/src/main/scala/Configs.scala

@@ -1,266 +0,0 @@
-package example
-
-import chisel3._
-
-import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache}
-
-import testchipip._
-
-// --------------
-// Rocket Configs
-// --------------
-
-class BaseRocketConfig extends Config(
-  new WithBootROM ++
-  new freechips.rocketchip.system.DefaultConfig)
-
-class DefaultRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new BaseRocketConfig)
-
-class HwachaConfig extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new DefaultRocketConfig)
-
-class RoccRocketConfig extends Config(
-  new WithRoccExample ++
-  new DefaultRocketConfig)
-
-class PWMRocketConfig extends Config(
-  new WithPWMBoomRocketTop ++
-  new BaseRocketConfig)
-
-class PWMAXI4RocketConfig extends Config(
-  new WithPWMAXI4BoomRocketTop ++
-  new BaseRocketConfig)
-
-class SimBlockDeviceRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithSimBlockDeviceBoomRocketTop ++
-  new BaseRocketConfig)
-
-class BlockDeviceModelRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithBlockDeviceModelBoomRocketTop ++
-  new BaseRocketConfig)
-
-class GPIORocketConfig extends Config(
-  new WithGPIO ++
-  new WithGPIOBoomRocketTop ++
-  new BaseRocketConfig)
-
-class DualCoreRocketConfig extends Config(
-  new WithNBigCores(2) ++
-  new DefaultRocketConfig)
-
-class RV32RocketConfig extends Config(
-  new WithRV32 ++
-  new DefaultRocketConfig)
-
-class GB1MemoryConfig extends Config(
-  new WithExtMemSize((1<<30) * 1L) ++
-  new DefaultRocketConfig)
-
-class RocketL2Config extends Config(
-  new WithInclusiveCache ++
-  new DefaultRocketConfig)
-
-class HwachaL2Config extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new WithInclusiveCache ++
-  new DefaultRocketConfig)
-
-// ------------
-// BOOM Configs
-// ------------
-
-class BaseBoomConfig extends Config(
-  new WithBootROM ++
-  new boom.common.LargeBoomConfig)
-
-class SmallBaseBoomConfig extends Config(
-  new WithBootROM ++
-  new boom.common.SmallBoomConfig)
-
-class DefaultBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new BaseBoomConfig)
-
-class SmallDefaultBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new SmallBaseBoomConfig)
-
-class HwachaBoomConfig extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new DefaultBoomConfig)
-
-class RoccBoomConfig extends Config(
-  new WithRoccExample ++
-  new DefaultBoomConfig)
-
-class PWMBoomConfig extends Config(
-  new WithPWMBoomRocketTop ++
-  new BaseBoomConfig)
-
-class PWMAXI4BoomConfig extends Config(
-  new WithPWMAXI4BoomRocketTop ++
-  new BaseBoomConfig)
-
-class SimBlockDeviceBoomConfig extends Config(
-  new WithBlockDevice ++
-  new WithSimBlockDeviceBoomRocketTop ++
-  new BaseBoomConfig)
-
-class BlockDeviceModelBoomConfig extends Config(
-  new WithBlockDevice ++
-  new WithBlockDeviceModelBoomRocketTop ++
-  new BaseBoomConfig)
-
-class GPIOBoomConfig extends Config(
-  new WithGPIO ++
-  new WithGPIOBoomRocketTop ++
-  new BaseBoomConfig)
-
-/**
- * Slightly different looking configs since we need to override
- * the `WithNBoomCores` with the DefaultBoomConfig params
- */
-class DualCoreBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualCoreSmallBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRVC ++
-  new boom.common.WithSmallBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class RV32UnifiedBoomConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.SmallRV32UnifiedBoomConfig)
-
-class BoomL2Config extends Config(
-  new WithInclusiveCache ++
-  new SmallDefaultBoomConfig)
-
-// ---------------------
-// BOOM and Rocket Configs
-// ---------------------
-
-class BaseBoomAndRocketConfig extends Config(
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class SmallBaseBoomAndRocketConfig extends Config(
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithRVC ++
-  new boom.common.WithSmallBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DefaultBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class SmallDefaultBoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new SmallBaseBoomAndRocketConfig)
-
-class HwachaBoomAndRocketConfig extends Config(
-  new hwacha.DefaultHwachaConfig ++
-  new DefaultBoomAndRocketConfig)
-
-class RoccBoomAndRocketConfig extends Config(
-  new WithRoccExample ++
-  new DefaultBoomAndRocketConfig)
-
-class PWMBoomAndRocketConfig extends Config(
-  new WithPWMBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class PWMAXI4BoomAndRocketConfig extends Config(
-  new WithPWMAXI4BoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class SimBlockDeviceBoomAndRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithSimBlockDeviceBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class BlockDeviceModelBoomAndRocketConfig extends Config(
-  new WithBlockDevice ++
-  new WithBlockDeviceModelBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class GPIOBoomAndRocketConfig extends Config(
-  new WithGPIO ++
-  new WithGPIOBoomRocketTop ++
-  new BaseBoomAndRocketConfig)
-
-class DualCoreBoomAndOneRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualBoomAndOneHwachaRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new WithMultiRoCC ++
-  new WithMultiRoCCHwacha(0) ++ // put Hwacha just on hart0 which was renumbered to Rocket
-  new boom.common.WithRenumberHarts(rocketFirst = true) ++
-  new hwacha.DefaultHwachaConfig ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(2) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class RV32BoomAndRocketConfig extends Config(
-  new WithNormalBoomRocketTop ++
-  new WithBootROM ++
-  new boom.common.WithRenumberHarts ++
-  new boom.common.WithBoomRV32 ++
-  new boom.common.WithRVC ++
-  new boom.common.WithLargeBooms ++
-  new boom.common.BaseBoomConfig ++
-  new boom.common.WithNBoomCores(1) ++
-  new freechips.rocketchip.subsystem.WithoutTLMonitors ++
-  new freechips.rocketchip.subsystem.WithRV32 ++
-  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
-  new freechips.rocketchip.system.BaseConfig)
-
-class DualCoreRocketL2Config extends Config(
-  new WithInclusiveCache ++
-  new DualCoreRocketConfig)

generators/example/src/main/scala/Generator.scala

@@ -4,6 +4,7 @@ import chisel3._
 
 import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
+import utilities.TestSuiteHelper
 
 object Generator extends GeneratorApp {
   // add unique test suites

generators/example/src/main/scala/HeteroConfigs.scala

@@ -0,0 +1,94 @@
+package example
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// ---------------------
+// Heterogenous Configs
+// ---------------------
+
+class LargeBoomAndRocketConfig extends Config(
+  new WithTop ++                                           // default top
+  new WithBootROM ++                                       // default bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use SiFive l2
+  new boom.common.WithRenumberHarts ++                     // avoid hartid overlap
+  new boom.common.WithLargeBooms ++                        // 3-wide boom
+  new boom.common.WithNBoomCores(1) ++                     // single-core boom
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single-core rocket
+  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
+
+class SmallBoomAndRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithSmallBooms ++                        // 1-wide boom
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class HwachaLargeBoomAndHwachaRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new hwacha.DefaultHwachaConfig ++                      // add hwacha to all harts
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class RoccLargeBoomAndRoccRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithRoccExample ++  // add example rocc accelerator to all harts
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualLargeBoomAndRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++                  // 2-boom cores
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualLargeBoomAndHwachaRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new WithMultiRoCC ++                                  // support heterogeneous rocc
+  new WithMultiRoCCHwacha(2) ++                         // put hwacha on hart-2 (rocket)
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class LargeBoomAndRV32RocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.subsystem.WithRV32 ++        // use 32-bit rocket
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualLargeBoomAndDualRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new boom.common.WithRenumberHarts ++
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(2) ++                   // 2 boom cores
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++ // 2 rocket cores
+  new freechips.rocketchip.system.BaseConfig)

generators/example/src/main/scala/InitZero.scala

@@ -0,0 +1,69 @@
+package example
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.subsystem.{BaseSubsystem, CacheBlockBytes}
+import freechips.rocketchip.config.{Parameters, Field}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, IdRange}
+import testchipip.TLHelper
+
+case class InitZeroConfig(base: BigInt, size: BigInt)
+case object InitZeroKey extends Field[InitZeroConfig]
+
+class InitZero(implicit p: Parameters) extends LazyModule {
+  val node = TLHelper.makeClientNode(
+    name = "init-zero", sourceId = IdRange(0, 1))
+
+  lazy val module = new InitZeroModuleImp(this)
+}
+
+class InitZeroModuleImp(outer: InitZero) extends LazyModuleImp(outer) {
+  val config = p(InitZeroKey)
+
+  val (mem, edge) = outer.node.out(0)
+  val addrBits = edge.bundle.addressBits
+  val blockBytes = p(CacheBlockBytes)
+
+  require(config.size % blockBytes == 0)
+
+  val s_init :: s_write :: s_resp :: s_done :: Nil = Enum(4)
+  val state = RegInit(s_init)
+
+  val addr = Reg(UInt(addrBits.W))
+  val bytesLeft = Reg(UInt(log2Ceil(config.size+1).W))
+
+  mem.a.valid := state === s_write
+  mem.a.bits := edge.Put(
+    fromSource = 0.U,
+    toAddress = addr,
+    lgSize = log2Ceil(blockBytes).U,
+    data = 0.U)._2
+  mem.d.ready := state === s_resp
+
+  when (state === s_init) {
+    addr := config.base.U
+    bytesLeft := config.size.U
+    state := s_write
+  }
+
+  when (edge.done(mem.a)) {
+    addr := addr + blockBytes.U
+    bytesLeft := bytesLeft - blockBytes.U
+    state := s_resp
+  }
+
+  when (mem.d.fire()) {
+    state := Mux(bytesLeft === 0.U, s_done, s_write)
+  }
+}
+
+trait HasPeripheryInitZero { this: BaseSubsystem =>
+  implicit val p: Parameters
+
+  val initZero = LazyModule(new InitZero()(p))
+  fbus.fromPort(Some("init-zero"))() := initZero.node
+}
+
+trait HasPeripheryInitZeroModuleImp extends LazyModuleImp {
+  // Don't need anything here
+}

generators/example/src/main/scala/NodeTypes.scala

@@ -0,0 +1,128 @@
+package example
+
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import testchipip.TLHelper
+
+// These modules are not meant to be synthesized.
+// They are used as examples in the documentation and are only here
+// to check that they compile.
+
+// DOC include start: MyClient
+class MyClient(implicit p: Parameters) extends LazyModule {
+  val node = TLHelper.makeClientNode(TLClientParameters(
+    name = "my-client",
+    sourceId = IdRange(0, 4),
+    requestFifo = true,
+    visibility = Seq(AddressSet(0x10000, 0xffff))))
+
+  lazy val module = new LazyModuleImp(this) {
+    val (tl, edge) = node.out(0)
+
+    // Rest of code here
+  }
+}
+// DOC include end: MyClient
+
+// DOC include start: MyManager
+class MyManager(implicit p: Parameters) extends LazyModule {
+  val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
+  val beatBytes = 8
+  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+    address = Seq(AddressSet(0x20000, 0xfff)),
+    resources = device.reg,
+    regionType = RegionType.UNCACHED,
+    executable = true,
+    supportsArithmetic = TransferSizes(1, beatBytes),
+    supportsLogical = TransferSizes(1, beatBytes),
+    supportsGet = TransferSizes(1, beatBytes),
+    supportsPutFull = TransferSizes(1, beatBytes),
+    supportsPutPartial = TransferSizes(1, beatBytes),
+    supportsHint = TransferSizes(1, beatBytes),
+    fifoId = Some(0)))
+
+  lazy val module = new LazyModuleImp(this) {
+    val (tl, edge) = node.in(0)
+  }
+}
+// DOC include end: MyManager
+
+// DOC include start: MyClient1+MyClient2
+class MyClient1(implicit p: Parameters) extends LazyModule {
+  val node = TLHelper.makeClientNode("my-client1", IdRange(0, 1))
+
+  lazy val module = new LazyModuleImp(this) {
+    // ...
+  }
+}
+
+class MyClient2(implicit p: Parameters) extends LazyModule {
+  val node = TLHelper.makeClientNode("my-client2", IdRange(0, 1))
+
+  lazy val module = new LazyModuleImp(this) {
+    // ...
+  }
+}
+// DOC include end: MyClient1+MyClient2
+
+// DOC include start: MyClientGroup
+class MyClientGroup(implicit p: Parameters) extends LazyModule {
+  val client1 = LazyModule(new MyClient1)
+  val client2 = LazyModule(new MyClient2)
+  val node = TLIdentityNode()
+
+  node := client1.node
+  node := client2.node
+
+  lazy val module = new LazyModuleImp(this) {
+    // Nothing to do here
+  }
+}
+// DOC include end: MyClientGroup
+
+// DOC include start: MyManagerGroup
+class MyManager1(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+    address = Seq(AddressSet(0x0, 0xfff))))
+
+  lazy val module = new LazyModuleImp(this) {
+    // ...
+  }
+}
+
+class MyManager2(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+  val node = TLHelper.makeManagerNode(beatBytes, TLManagerParameters(
+    address = Seq(AddressSet(0x1000, 0xfff))))
+
+  lazy val module = new LazyModuleImp(this) {
+    // ...
+  }
+}
+
+class MyManagerGroup(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+  val man1 = LazyModule(new MyManager1(beatBytes))
+  val man2 = LazyModule(new MyManager2(beatBytes))
+  val node = TLIdentityNode()
+
+  man1.node := node
+  man2.node := node
+
+  lazy val module = new LazyModuleImp(this) {
+    // Nothing to do here
+  }
+}
+// DOC include end: MyManagerGroup
+
+// DOC include start: MyClientManagerComplex
+class MyClientManagerComplex(implicit p: Parameters) extends LazyModule {
+  val client = LazyModule(new MyClientGroup)
+  val manager = LazyModule(new MyManagerGroup(8))
+
+  manager.node :=* client.node
+
+  lazy val module = new LazyModuleImp(this) {
+    // Nothing to do here
+  }
+}
+// DOC include end: MyClientManagerComplex

generators/example/src/main/scala/PWM.scala

@@ -10,6 +10,7 @@ import freechips.rocketchip.regmapper.{HasRegMap, RegField}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.util.UIntIsOneOf
 
+// DOC include start: PWM generic traits
 case class PWMParams(address: BigInt, beatBytes: Int)
 
 class PWMBase(w: Int) extends Module {
@@ -64,19 +65,23 @@ trait PWMModule extends HasRegMap {
     0x08 -> Seq(
       RegField(1, enable)))
 }
+// DOC include end: PWM generic traits
 
+// DOC include start: PWMTL
 class PWMTL(c: PWMParams)(implicit p: Parameters)
   extends TLRegisterRouter(
     c.address, "pwm", Seq("ucbbar,pwm"),
     beatBytes = c.beatBytes)(
       new TLRegBundle(c, _) with PWMBundle)(
       new TLRegModule(c, _, _) with PWMModule)
+// DOC include end: PWMTL
 
 class PWMAXI4(c: PWMParams)(implicit p: Parameters)
   extends AXI4RegisterRouter(c.address, beatBytes = c.beatBytes)(
       new AXI4RegBundle(c, _) with PWMBundle)(
       new AXI4RegModule(c, _, _) with PWMModule)
 
+// DOC include start: HasPeripheryPWMTL
 trait HasPeripheryPWMTL { this: BaseSubsystem =>
   implicit val p: Parameters
 
@@ -88,7 +93,9 @@ trait HasPeripheryPWMTL { this: BaseSubsystem =>
 
   pbus.toVariableWidthSlave(Some(portName)) { pwm.node }
 }
+// DOC include end: HasPeripheryPWMTL
 
+// DOC include start: HasPeripheryPWMTLModuleImp
 trait HasPeripheryPWMTLModuleImp extends LazyModuleImp {
   implicit val p: Parameters
   val outer: HasPeripheryPWMTL
@@ -97,6 +104,7 @@ trait HasPeripheryPWMTLModuleImp extends LazyModuleImp {
 
   pwmout := outer.pwm.module.io.pwmout
 }
+// DOC include end: HasPeripheryPWMTLModuleImp
 
 trait HasPeripheryPWMAXI4 { this: BaseSubsystem =>
   implicit val p: Parameters

generators/example/src/main/scala/RegisterNodeExample.scala

@@ -0,0 +1,181 @@
+// DOC include start: MyDeviceController
+
+import chisel3._
+import chisel3.util._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.regmapper._
+import freechips.rocketchip.tilelink.TLRegisterNode
+
+class MyDeviceController(implicit p: Parameters) extends LazyModule {
+  val device = new SimpleDevice("my-device", Seq("tutorial,my-device0"))
+  val node = TLRegisterNode(
+    address = Seq(AddressSet(0x10028000, 0xfff)),
+    device = device,
+    beatBytes = 8,
+    concurrency = 1)
+
+  lazy val module = new LazyModuleImp(this) {
+    val bigReg = RegInit(0.U(64.W))
+    val mediumReg = RegInit(0.U(32.W))
+    val smallReg = RegInit(0.U(16.W))
+
+    val tinyReg0 = RegInit(0.U(4.W))
+    val tinyReg1 = RegInit(0.U(4.W))
+
+    node.regmap(
+      0x00 -> Seq(RegField(64, bigReg)),
+      0x08 -> Seq(RegField(32, mediumReg)),
+      0x0C -> Seq(RegField(16, smallReg)),
+      0x0E -> Seq(
+        RegField(4, tinyReg0),
+        RegField(4, tinyReg1)))
+  }
+}
+
+// DOC include end: MyDeviceController
+
+// DOC include start: MyAXI4DeviceController
+import freechips.rocketchip.amba.axi4.AXI4RegisterNode
+
+class MyAXI4DeviceController(implicit p: Parameters) extends LazyModule {
+  val node = AXI4RegisterNode(
+    address = AddressSet(0x10029000, 0xfff),
+    beatBytes = 8,
+    concurrency = 1)
+
+  lazy val module = new LazyModuleImp(this) {
+    val bigReg = RegInit(0.U(64.W))
+    val mediumReg = RegInit(0.U(32.W))
+    val smallReg = RegInit(0.U(16.W))
+
+    val tinyReg0 = RegInit(0.U(4.W))
+    val tinyReg1 = RegInit(0.U(4.W))
+
+    node.regmap(
+      0x00 -> Seq(RegField(64, bigReg)),
+      0x08 -> Seq(RegField(32, mediumReg)),
+      0x0C -> Seq(RegField(16, smallReg)),
+      0x0E -> Seq(
+        RegField(4, tinyReg0),
+        RegField(4, tinyReg1)))
+  }
+}
+// DOC include end: MyAXI4DeviceController
+
+class MyQueueRegisters(implicit p: Parameters) extends LazyModule {
+  val device = new SimpleDevice("my-queue", Seq("tutorial,my-queue0"))
+  val node = TLRegisterNode(
+    address = Seq(AddressSet(0x1002A000, 0xfff)),
+    device = device,
+    beatBytes = 8,
+    concurrency = 1)
+
+  lazy val module = new LazyModuleImp(this) {
+// DOC include start: MyQueueRegisters
+    // 4-entry 64-bit queue
+    val queue = Module(new Queue(UInt(64.W), 4))
+
+    node.regmap(
+      0x00 -> Seq(RegField(64, queue.io.deq, queue.io.enq)))
+// DOC include end: MyQueueRegisters
+  }
+}
+
+class MySeparateQueueRegisters(implicit p: Parameters) extends LazyModule {
+  val device = new SimpleDevice("my-queue", Seq("tutorial,my-queue1"))
+  val node = TLRegisterNode(
+    address = Seq(AddressSet(0x1002B000, 0xfff)),
+    device = device,
+    beatBytes = 8,
+    concurrency = 1)
+
+  lazy val module = new LazyModuleImp(this) {
+    val queue = Module(new Queue(UInt(64.W), 4))
+
+// DOC include start: MySeparateQueueRegisters
+    node.regmap(
+      0x00 -> Seq(RegField.r(64, queue.io.deq)),
+      0x08 -> Seq(RegField.w(64, queue.io.enq)))
+// DOC include end: MySeparateQueueRegisters
+  }
+}
+
+class MyCounterRegisters(implicit p: Parameters) extends LazyModule {
+  val device = new SimpleDevice("my-counters", Seq("tutorial,my-counters0"))
+  val node = TLRegisterNode(
+    address = Seq(AddressSet(0x1002C000, 0xfff)),
+    device = device,
+    beatBytes = 8,
+    concurrency = 1)
+
+  lazy val module = new LazyModuleImp(this) {
+// DOC include start: MyCounterRegisters
+    val counter = RegInit(0.U(64.W))
+
+    def readCounter(ready: Bool): (Bool, UInt) = {
+      when (ready) { counter := counter - 1.U }
+      // (ready, bits)
+      (true.B, counter)
+    }
+
+    def writeCounter(valid: Bool, bits: UInt): Bool = {
+      when (valid) { counter := counter + 1.U }
+      // Ignore bits
+      // Return ready
+      true.B
+    }
+
+    node.regmap(
+      0x00 -> Seq(RegField.r(64, readCounter(_))),
+      0x08 -> Seq(RegField.w(64, writeCounter(_, _))))
+// DOC include end: MyCounterRegisters
+  }
+}
+
+class MyCounterReqRespRegisters(implicit p: Parameters) extends LazyModule {
+  val device = new SimpleDevice("my-counters", Seq("tutorial,my-counters1"))
+  val node = TLRegisterNode(
+    address = Seq(AddressSet(0x1002D000, 0xfff)),
+    device = device,
+    beatBytes = 8,
+    concurrency = 1)
+
+  lazy val module = new LazyModuleImp(this) {
+// DOC include start: MyCounterReqRespRegisters
+    val counter = RegInit(0.U(64.W))
+
+    def readCounter(ivalid: Bool, oready: Bool): (Bool, Bool, UInt) = {
+      val responding = RegInit(false.B)
+
+      when (ivalid && !responding) { responding := true.B }
+
+      when (responding && oready) {
+        counter := counter - 1.U
+        responding := false.B
+      }
+
+      // (iready, ovalid, obits)
+      (!responding, responding, counter)
+    }
+
+    def writeCounter(ivalid: Bool, oready: Bool, ibits: UInt): (Bool, Bool) = {
+      val responding = RegInit(false.B)
+
+      when (ivalid && !responding) { responding := true.B }
+
+      when (responding && oready) {
+        counter := counter + 1.U
+        responding := false.B
+      }
+
+      // (iready, ovalid)
+      (!responding, responding)
+    }
+
+    node.regmap(
+      0x00 -> Seq(RegField.r(64, readCounter(_, _))),
+      0x08 -> Seq(RegField.w(64, writeCounter(_, _, _))))
+// DOC include end: MyCounterReqRespRegisters
+  }
+}

generators/example/src/main/scala/RocketConfigs.scala

@@ -0,0 +1,121 @@
+package example
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+// --------------
+// Rocket Configs
+// --------------
+
+class RocketConfig extends Config(
+  new WithTop ++                                           // use default top
+  new WithBootROM ++                                       // use default bootrom
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++   // single rocket-core
+  new freechips.rocketchip.system.BaseConfig)              // "base" rocketchip system
+
+class HwachaRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new hwacha.DefaultHwachaConfig ++                        // use Hwacha vector accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class RoccRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithRoccExample ++    // use example RoCC-based accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class jtagRocketConfig extends Config(
+  new WithDTMTop ++                                        // use top with dtm
+  new freechips.rocketchip.subsystem.WithJtagDTM ++        // add jtag/DTM module to coreplex
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: PWMRocketConfig
+class PWMRocketConfig extends Config(
+  new WithPWMTop ++                                        // use top with tilelink-controlled PWM
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: PWMRocketConfig
+
+class PWMRAXI4ocketConfig extends Config(
+  new WithPWMAXI4Top ++                                    // use top with axi4-controlled PWM
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class SimBlockDeviceRocketConfig extends Config(
+  new testchipip.WithBlockDevice ++                        // add block-device module to peripherybus
+  new WithSimBlockDeviceTop ++                             // use top with block-device IOs and connect to simblockdevice
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class BlockDeviceModelRocketConfig extends Config(
+  new testchipip.WithBlockDevice ++                        // add block-device module to periphery bus
+  new WithBlockDeviceModelTop ++                           // use top with block-device IOs and connect to a blockdevicemodel
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class GPIORocketConfig extends Config(
+  new WithGPIO ++                                          // add GPIOs to the peripherybus
+  new WithGPIOTop ++                                       // use top with GPIOs
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class DualCoreRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(2) ++   // dual-core (2 RocketTiles)
+  new freechips.rocketchip.system.BaseConfig)
+
+class RV32RocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithRV32 ++           // set RocketTiles to be 32-bit
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class GB1MemoryRocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithExtMemSize((1<<30) * 1L) ++ // use 2GB simulated external memory
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+class Sha3RocketConfig extends Config(
+  new WithTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new sha3.WithSha3Accel ++                                // add SHA3 rocc accelerator
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+
+// DOC include start: InitZeroRocketConfig
+class InitZeroRocketConfig extends Config(
+  new WithInitZero(0x88000000L, 0x1000L) ++
+  new WithInitZeroTop ++
+  new WithBootROM ++
+  new freechips.rocketchip.subsystem.WithInclusiveCache ++
+  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
+  new freechips.rocketchip.system.BaseConfig)
+// DOC include end: InitZeroRocketConfig

generators/example/src/main/scala/TestHarness.scala

@@ -14,8 +14,8 @@ import freechips.rocketchip.devices.debug.{Debug}
 // BOOM and/or Rocket Test Harness
 // -------------------------------
 
-case object BuildBoomRocketTop extends Field[(Clock, Bool, Parameters) => BoomRocketTopModule[BoomRocketTop]]
-case object BuildBoomRocketTopWithDTM extends Field[(Clock, Bool, Parameters) => BoomRocketTopWithDTMModule[BoomRocketTopWithDTM]]
+case object BuildTop extends Field[(Clock, Bool, Parameters) => TopModule[Top]]
+case object BuildTopWithDTM extends Field[(Clock, Bool, Parameters) => TopWithDTMModule[TopWithDTM]]
 
 /**
  * Test harness using TSI to bringup the system
@@ -28,7 +28,7 @@ class TestHarness(implicit val p: Parameters) extends Module {
   // force Chisel to rename module
   override def desiredName = "TestHarness"
 
-  val dut = p(BuildBoomRocketTop)(clock, reset.toBool, p)
+  val dut = p(BuildTop)(clock, reset.toBool, p)
 
   dut.debug := DontCare
   dut.connectSimAXIMem()
@@ -63,7 +63,7 @@ class TestHarnessWithDTM(implicit p: Parameters) extends Module
   // force Chisel to rename module
   override def desiredName = "TestHarness"
 
-  val dut = p(BuildBoomRocketTopWithDTM)(clock, reset.toBool, p)
+  val dut = p(BuildTopWithDTM)(clock, reset.toBool, p)
 
   dut.reset := reset.asBool | dut.debug.ndreset
   dut.connectSimAXIMem()

generators/example/src/main/scala/Top.scala

@@ -10,69 +10,84 @@ import freechips.rocketchip.util.DontTouch
 
 import testchipip._
 
+import utilities.{System, SystemModule}
+
 import sifive.blocks.devices.gpio._
 
 // ------------------------------------
 // BOOM and/or Rocket Top Level Systems
 // ------------------------------------
 
-class BoomRocketTop(implicit p: Parameters) extends boom.system.BoomRocketSystem
+class Top(implicit p: Parameters) extends System
   with HasNoDebug
   with HasPeripherySerial {
-  override lazy val module = new BoomRocketTopModule(this)
+  override lazy val module = new TopModule(this)
 }
 
-class BoomRocketTopModule[+L <: BoomRocketTop](l: L) extends boom.system.BoomRocketSystemModule(l)
+class TopModule[+L <: Top](l: L) extends SystemModule(l)
   with HasNoDebugModuleImp
   with HasPeripherySerialModuleImp
   with DontTouch
 
 //---------------------------------------------------------------------------------------------------------
+// DOC include start: TopWithPWMTL
 
-class BoomRocketTopWithPWMTL(implicit p: Parameters) extends BoomRocketTop
+class TopWithPWMTL(implicit p: Parameters) extends Top
   with HasPeripheryPWMTL {
-  override lazy val module = new BoomRocketTopWithPWMTLModule(this)
+  override lazy val module = new TopWithPWMTLModule(this)
 }
 
-class BoomRocketTopWithPWMTLModule(l: BoomRocketTopWithPWMTL) extends BoomRocketTopModule(l)
+class TopWithPWMTLModule(l: TopWithPWMTL) extends TopModule(l)
   with HasPeripheryPWMTLModuleImp
 
+// DOC include end: TopWithPWMTL
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithPWMAXI4(implicit p: Parameters) extends BoomRocketTop
+class TopWithPWMAXI4(implicit p: Parameters) extends Top
   with HasPeripheryPWMAXI4 {
-  override lazy val module = new BoomRocketTopWithPWMAXI4Module(this)
+  override lazy val module = new TopWithPWMAXI4Module(this)
 }
 
-class BoomRocketTopWithPWMAXI4Module(l: BoomRocketTopWithPWMAXI4) extends BoomRocketTopModule(l)
+class TopWithPWMAXI4Module(l: TopWithPWMAXI4) extends TopModule(l)
   with HasPeripheryPWMAXI4ModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithBlockDevice(implicit p: Parameters) extends BoomRocketTop
+class TopWithBlockDevice(implicit p: Parameters) extends Top
   with HasPeripheryBlockDevice {
-  override lazy val module = new BoomRocketTopWithBlockDeviceModule(this)
+  override lazy val module = new TopWithBlockDeviceModule(this)
 }
 
-class BoomRocketTopWithBlockDeviceModule(l: BoomRocketTopWithBlockDevice) extends BoomRocketTopModule(l)
+class TopWithBlockDeviceModule(l: TopWithBlockDevice) extends TopModule(l)
   with HasPeripheryBlockDeviceModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithGPIO(implicit p: Parameters) extends BoomRocketTop
-    with HasPeripheryGPIO {
-  override lazy val module = new BoomRocketTopWithGPIOModule(this)
+class TopWithGPIO(implicit p: Parameters) extends Top
+  with HasPeripheryGPIO {
+  override lazy val module = new TopWithGPIOModule(this)
 }
 
-class BoomRocketTopWithGPIOModule(l: BoomRocketTopWithGPIO)
-  extends BoomRocketTopModule(l)
+class TopWithGPIOModule(l: TopWithGPIO)
+  extends TopModule(l)
   with HasPeripheryGPIOModuleImp
 
 //---------------------------------------------------------------------------------------------------------
 
-class BoomRocketTopWithDTM(implicit p: Parameters) extends boom.system.BoomRocketSystem
+class TopWithDTM(implicit p: Parameters) extends System
 {
-  override lazy val module = new BoomRocketTopWithDTMModule(this)
+  override lazy val module = new TopWithDTMModule(this)
 }
 
-class BoomRocketTopWithDTMModule[+L <: BoomRocketTopWithDTM](l: L) extends boom.system.BoomRocketSystemModule(l)
+class TopWithDTMModule[+L <: TopWithDTM](l: L) extends SystemModule(l)
+
+//---------------------------------------------------------------------------------------------------------
+// DOC include start: TopWithInitZero
+class TopWithInitZero(implicit p: Parameters) extends Top
+    with HasPeripheryInitZero {
+  override lazy val module = new TopWithInitZeroModuleImp(this)
+}
+
+class TopWithInitZeroModuleImp(l: TopWithInitZero) extends TopModule(l)
+  with HasPeripheryInitZeroModuleImp
+// DOC include end: TopWithInitZero

generators/firechip/src/main/scala/Generator.scala

@@ -16,80 +16,14 @@ import freechips.rocketchip.config.Parameters
 import freechips.rocketchip.subsystem.RocketTilesKey
 import freechips.rocketchip.tile.XLen
 
-import boom.system.{BoomTilesKey, BoomTestSuites}
-
 import firesim.util.{GeneratorArgs, HasTargetAgnosticUtilites, HasFireSimGeneratorUtilities}
 
+import utilities.TestSuiteHelper
+
 trait HasTestSuites {
-  val rv64RegrTestNames = collection.mutable.LinkedHashSet(
-      "rv64ud-v-fcvt",
-      "rv64ud-p-fdiv",
-      "rv64ud-v-fadd",
-      "rv64uf-v-fadd",
-      "rv64um-v-mul",
-      // "rv64mi-p-breakpoint", // Not implemented in BOOM
-      // "rv64uc-v-rvc", // Not implemented in BOOM
-      "rv64ud-v-structural",
-      "rv64si-p-wfi",
-      "rv64um-v-divw",
-      "rv64ua-v-lrsc",
-      "rv64ui-v-fence_i",
-      "rv64ud-v-fcvt_w",
-      "rv64uf-v-fmin",
-      "rv64ui-v-sb",
-      "rv64ua-v-amomax_d",
-      "rv64ud-v-move",
-      "rv64ud-v-fclass",
-      "rv64ua-v-amoand_d",
-      "rv64ua-v-amoxor_d",
-      "rv64si-p-sbreak",
-      "rv64ud-v-fmadd",
-      "rv64uf-v-ldst",
-      "rv64um-v-mulh",
-      "rv64si-p-dirty")
-
-  val rv32RegrTestNames = collection.mutable.LinkedHashSet(
-      "rv32mi-p-ma_addr",
-      "rv32mi-p-csr",
-      "rv32ui-p-sh",
-      "rv32ui-p-lh",
-      "rv32uc-p-rvc",
-      "rv32mi-p-sbreak",
-      "rv32ui-p-sll")
-
   def addTestSuites(targetName: String, params: Parameters) {
-    val coreParams =
-      if (params(RocketTilesKey).nonEmpty) {
-        params(RocketTilesKey).head.core
-      } else {
-        params(BoomTilesKey).head.core
-      }
-    val xlen = params(XLen)
-    val vm = coreParams.useVM
-    val env = if (vm) List("p","v") else List("p")
-    coreParams.fpu foreach { case cfg =>
-      if (xlen == 32) {
-        TestGeneration.addSuites(env.map(rv32uf))
-        if (cfg.fLen >= 64)
-          TestGeneration.addSuites(env.map(rv32ud))
-      } else {
-        TestGeneration.addSuite(rv32udBenchmarks)
-        TestGeneration.addSuites(env.map(rv64uf))
-        if (cfg.fLen >= 64)
-          TestGeneration.addSuites(env.map(rv64ud))
-      }
-    }
-    if (coreParams.useAtomics)    TestGeneration.addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-    if (coreParams.useCompressed) TestGeneration.addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-    val (rvi, rvu) =
-      if (params(BoomTilesKey).nonEmpty) ((if (vm) BoomTestSuites.rv64i else BoomTestSuites.rv64pi), rv64u)
-      else if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-      else            ((if (vm) rv32i else rv32pi), rv32u)
-
-    TestGeneration.addSuites(rvi.map(_("p")))
-    TestGeneration.addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-    TestGeneration.addSuite(benchmarks)
-    TestGeneration.addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
+    TestSuiteHelper.addRocketTestSuites(params)
+    TestSuiteHelper.addBoomTestSuites(params)
     TestGeneration.addSuite(FastBlockdevTests)
     TestGeneration.addSuite(SlowBlockdevTests)
     if (!targetName.contains("NoNIC"))

generators/firechip/src/main/scala/TargetConfigs.scala

@@ -4,14 +4,18 @@ import java.io.File
 
 import chisel3.util.{log2Up}
 import freechips.rocketchip.config.{Parameters, Config}
+import freechips.rocketchip.groundtest.TraceGenParams
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.rocket.DCacheParams
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.DebugModuleParams
-import boom.system.BoomTilesKey
+import boom.common.BoomTilesKey
 import testchipip.{BlockDeviceKey, BlockDeviceConfig}
 import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
+import scala.math.{min, max}
+import tracegen.TraceGenKey
 import icenet._
 
 import firesim.endpoints._
@@ -143,8 +147,10 @@ class FireSimBoomConfig extends Config(
   new WithBoomL2TLBs(1024) ++
   new WithoutClockGating ++
   new WithDefaultMemModel ++
-  // Using a small config because it has 64-bit system bus, and compiles quickly
-  new boom.system.SmallBoomConfig)
+  new boom.common.WithLargeBooms ++
+  new boom.common.WithNBoomCores(1) ++
+  new freechips.rocketchip.system.BaseConfig
+)
 
 // A safer implementation than the one in BOOM in that it
 // duplicates whatever BOOMTileKey.head is present N times. This prevents
@@ -210,3 +216,69 @@ class SupernodeFireSimRocketChipOctaCoreConfig extends Config(
   new WithExtMemSize(0x200000000L) ++ // 8GB
   new FireSimRocketChipOctaCoreConfig)
 
+class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+    extends Config((site, here, up) => {
+  case TraceGenKey => params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val nSets = dcp.nSets
+      val nWays = dcp.nWays
+      val blockOffset = site(SystemBusKey).blockOffset
+      val nBeats = min(2, site(SystemBusKey).blockBeats)
+      val beatBytes = site(SystemBusKey).beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => log2Up(params.size)
+})
+
+class FireSimTraceGenConfig extends Config(
+  new WithTraceGen(
+    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new FireSimRocketChipConfig)
+
+class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+    extends Config((site, here, up) => {
+  case TraceGenKey => params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val sbp = site(SystemBusKey)
+      val l2p = site(InclusiveCacheKey)
+      val nSets = max(l2p.sets, dcp.nSets)
+      val nWays = max(l2p.ways, dcp.nWays)
+      val nBanks = site(BankedL2Key).nBanks
+      val blockOffset = sbp.blockOffset
+      val nBeats = min(2, sbp.blockBeats)
+      val beatBytes = sbp.beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets * nBanks) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => log2Up(params.size)
+})
+
+class FireSimTraceGenL2Config extends Config(
+  new WithL2TraceGen(
+    List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new WithInclusiveCache(
+    nBanks = 4,
+    capacityKB = 1024,
+    outerLatencyCycles = 50) ++
+  new FireSimRocketChipConfig)

generators/firechip/src/main/scala/TargetMixins.scala

@@ -74,10 +74,10 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
   ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
 }
 
-trait CanHaveBoomMultiCycleRegfileImp {
-  val outer: boom.system.BoomRocketSubsystem
-  val cores = outer.boomTiles.map(tile => tile.module.core)
-  cores.foreach({ core =>
+trait CanHaveMultiCycleRegfileImp {
+  val outer: utilities.HasBoomAndRocketTiles
+  val boomCores = outer.boomTiles.map(tile => tile.module.core)
+  boomCores.foreach({ core =>
     core.iregfile match {
       case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
       case _ => Nil
@@ -87,11 +87,8 @@ trait CanHaveBoomMultiCycleRegfileImp {
       case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
       case _ => Nil
     }
+  })
 
-   })
-}
-trait CanHaveRocketMultiCycleRegfileImp {
-  val outer: RocketSubsystem
   outer.rocketTiles.foreach({ tile =>
     annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
     tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))

generators/firechip/src/main/scala/Targets.scala

@@ -12,10 +12,11 @@ import freechips.rocketchip.util.{HeterogeneousBag}
 import freechips.rocketchip.amba.axi4.AXI4Bundle
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy.LazyModule
-import boom.system.{BoomRocketSubsystem, BoomRocketSubsystemModuleImp}
+import utilities.{Subsystem, SubsystemModuleImp}
 import icenet._
 import testchipip._
 import testchipip.SerialAdapter.SERIAL_IF_WIDTH
+import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
 import sifive.blocks.devices.uart._
 import java.io.File
 
@@ -36,8 +37,8 @@ import FireSimValName._
 * determine which driver to build.
 *******************************************************************************/
 
-class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
-    with HasDefaultBusConfiguration
+class FireSimDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasPeripherySerial
@@ -49,7 +50,7 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem
   override lazy val module = new FireSimModuleImp(this)
 }
 
-class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l)
+class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -58,12 +59,12 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(
     with HasPeripheryIceNICModuleImpValidOnly
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
-    with CanHaveRocketMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp
 
 class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)
 
-class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
-    with HasDefaultBusConfiguration
+class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasPeripherySerial
@@ -74,7 +75,7 @@ class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem
   override lazy val module = new FireSimNoNICModuleImp(this)
 }
 
-class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l)
+class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -82,13 +83,13 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
-    with CanHaveRocketMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp
 
 
 class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT)
 
-class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasDefaultBusConfiguration
+class FireBoomDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasPeripherySerial
@@ -100,7 +101,7 @@ class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem
   override lazy val module = new FireBoomModuleImp(this)
 }
 
-class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l)
+class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -110,12 +111,12 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
-    with CanHaveBoomMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp
 
 class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT)
 
-class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
-    with HasDefaultBusConfiguration
+class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
+    with HasHierarchicalBusTopology
     with CanHaveMasterAXI4MemPort
     with HasPeripheryBootROM
     with HasPeripherySerial
@@ -126,7 +127,7 @@ class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem
   override lazy val module = new FireBoomNoNICModuleImp(this)
 }
 
-class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l)
+class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModuleImp(l)
     with HasRTCModuleImp
     with CanHaveMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
@@ -135,9 +136,20 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
-    with CanHaveBoomMultiCycleRegfileImp
+    with CanHaveMultiCycleRegfileImp
 
 class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT)
 
+class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
+    with HasHierarchicalBusTopology
+    with HasTraceGenTiles
+    with CanHaveMasterAXI4MemPort {
+  override lazy val module = new FireSimTraceGenModuleImp(this)
+}
+
+class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModuleImp(outer)
+    with HasTraceGenTilesModuleImp
+    with CanHaveMasterAXI4MemPortModuleImp
+
 // Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1
 class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT)

generators/tracegen/src/main/scala/Configs.scala

@@ -0,0 +1,76 @@
+package tracegen
+
+import chisel3._
+import chisel3.util.log2Ceil
+import freechips.rocketchip.config.{Config, Parameters}
+import freechips.rocketchip.groundtest.{TraceGenParams}
+import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey}
+import freechips.rocketchip.system.BaseConfig
+import freechips.rocketchip.rocket.DCacheParams
+import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
+import scala.math.{max, min}
+
+class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+    extends Config((site, here, up) => {
+  case TraceGenKey => params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val nSets = dcp.nSets
+      val nWays = dcp.nWays
+      val blockOffset = site(SystemBusKey).blockOffset
+      val nBeats = min(2, site(SystemBusKey).blockBeats)
+      val beatBytes = site(SystemBusKey).beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
+})
+
+class TraceGenConfig extends Config(
+  new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
+  new BaseConfig)
+
+class NonBlockingTraceGenConfig extends Config(
+  new WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
+  new BaseConfig)
+
+class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192)
+    extends Config((site, here, up) => {
+  case TraceGenKey => params.map { dcp => TraceGenParams(
+    dcache = Some(dcp),
+    wordBits = site(XLen),
+    addrBits = 48,
+    addrBag = {
+      val sbp = site(SystemBusKey)
+      val l2p = site(InclusiveCacheKey)
+      val nSets = max(l2p.sets, dcp.nSets)
+      val nWays = max(l2p.ways, dcp.nWays)
+      val blockOffset = sbp.blockOffset
+      val nBeats = min(2, sbp.blockBeats)
+      val beatBytes = sbp.beatBytes
+      List.tabulate(2 * nWays) { i =>
+        Seq.tabulate(nBeats) { j =>
+          BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
+        }
+      }.flatten
+    },
+    maxRequests = nReqs,
+    memStart = site(ExtMem).get.master.base,
+    numGens = params.size)
+  }
+  case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
+})
+
+class NonBlockingTraceGenL2Config extends Config(
+  new WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
+  new WithInclusiveCache ++
+  new BaseConfig)

generators/tracegen/src/main/scala/System.scala

@@ -0,0 +1,43 @@
+package tracegen
+
+import chisel3._
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
+import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams}
+import freechips.rocketchip.subsystem._
+
+case object TraceGenKey extends Field[Seq[TraceGenParams]]
+
+trait HasTraceGenTiles { this: BaseSubsystem =>
+  val tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
+    LazyModule(new TraceGenTile(i, params, p))
+  }
+
+  tiles.foreach { t =>
+    sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode }
+  }
+}
+
+trait HasTraceGenTilesModuleImp extends LazyModuleImp {
+  val outer: HasTraceGenTiles
+  val success = IO(Output(Bool()))
+
+  outer.tiles.zipWithIndex.map { case(t, i) =>
+    t.module.constants.hartid := i.U
+  }
+
+  val status = DebugCombiner(outer.tiles.map(_.module.status))
+  success := status.finished
+}
+
+class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
+    with HasTraceGenTiles
+    with HasHierarchicalBusTopology
+    with CanHaveMasterAXI4MemPort {
+  override lazy val module = new TraceGenSystemModuleImp(this)
+}
+
+class TraceGenSystemModuleImp(outer: TraceGenSystem)
+  extends BaseSubsystemModuleImp(outer)
+  with HasTraceGenTilesModuleImp
+  with CanHaveMasterAXI4MemPortModuleImp

generators/tracegen/src/main/scala/TestHarness.scala

@@ -0,0 +1,27 @@
+package tracegen
+
+import chisel3._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.LazyModule
+import freechips.rocketchip.util.GeneratorApp
+
+class TestHarness(implicit p: Parameters) extends Module {
+  val io = IO(new Bundle {
+    val success = Output(Bool())
+  })
+
+  val dut = Module(LazyModule(new TraceGenSystem).module)
+  io.success := dut.success
+  dut.connectSimAXIMem()
+}
+
+object Generator extends GeneratorApp {
+  // specify the name that the generator outputs files as
+  val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
+
+  // generate files
+  generateFirrtl
+  generateAnno
+  generateTestSuiteMakefrags
+  generateArtefacts
+}

generators/tracegen/src/main/scala/Tile.scala

@@ -0,0 +1,53 @@
+package tracegen
+
+import chisel3._
+import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing}
+import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus}
+import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF}
+import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate}
+import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode}
+import freechips.rocketchip.interrupts._
+
+class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters)
+    extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) {
+  val dcache = params.dcache.map { dc => LazyModule(
+    if (dc.nMSHRs == 0) new DCache(hartId, crossing)
+    else new NonBlockingDCache(hartId))
+  }.get
+
+  val intInwardNode: IntInwardNode = IntIdentityNode()
+  val intOutwardNode: IntOutwardNode = IntIdentityNode()
+  val slaveNode: TLInwardNode = TLIdentityNode()
+  val ceaseNode: IntOutwardNode = IntIdentityNode()
+  val haltNode: IntOutwardNode = IntIdentityNode()
+  val wfiNode: IntOutwardNode = IntIdentityNode()
+
+  val masterNode = visibilityNode
+  masterNode := dcache.node
+
+  override lazy val module = new TraceGenTileModuleImp(this)
+}
+
+class TraceGenTileModuleImp(outer: TraceGenTile)
+    extends BaseTileModuleImp(outer) {
+  val status = IO(new GroundTestStatus)
+  val halt_and_catch_fire = None
+
+  val ptw = Module(new DummyPTW(1))
+  ptw.io.requestors.head <> outer.dcache.module.io.ptw
+
+  val tracegen = Module(new TraceGenerator(outer.params))
+  tracegen.io.hartid := constants.hartid
+
+  val dcacheIF = Module(new SimpleHellaCacheIF())
+  dcacheIF.io.requestor <> tracegen.io.mem
+  outer.dcache.module.io.cpu <> dcacheIF.io.cache
+
+  status.finished := tracegen.io.finished
+  status.timeout.valid := tracegen.io.timeout
+  status.timeout.bits := 0.U
+  status.error.valid := false.B
+
+  assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out")
+}

generators/utilities/src/main/scala/Subsystem.scala

@@ -0,0 +1,108 @@
+//******************************************************************************
+// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
+// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
+//------------------------------------------------------------------------------
+
+package utilities
+
+import chisel3._
+import chisel3.internal.sourceinfo.{SourceInfo}
+
+import freechips.rocketchip.config.{Field, Parameters}
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
+import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
+import freechips.rocketchip.tile._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
+import freechips.rocketchip.util._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.amba.axi4._
+
+import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey}
+
+
+trait HasBoomAndRocketTiles extends HasTiles
+  with CanHavePeripheryPLIC
+  with CanHavePeripheryCLINT
+  with HasPeripheryDebug
+{ this: BaseSubsystem =>
+
+  val module: HasBoomAndRocketTilesModuleImp
+
+  protected val rocketTileParams = p(RocketTilesKey)
+  protected val boomTileParams = p(BoomTilesKey)
+  // crossing can either be per tile or global (aka only 1 crossing specified)
+  private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
+  private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
+
+  // Make a tile and wire its nodes into the system,
+  // according to the specified type of clock crossing.
+  // Note that we also inject new nodes into the tile itself,
+  // also based on the crossing type.
+  val rocketTiles = rocketTileParams.zip(rocketCrossings).map { case (tp, crossing) =>
+    val rocket = LazyModule(new RocketTile(tp, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
+
+    connectMasterPortsToSBus(rocket, crossing)
+    connectSlavePortsToCBus(rocket, crossing)
+
+    def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(rocket.rocketLogicalTree.getOMInterruptTargets)
+    LogicalModuleTree.add(logicalTreeNode, rocket.rocketLogicalTree)
+
+    rocket
+  }
+
+  val boomTiles = boomTileParams.zip(boomCrossings).map { case (tp, crossing) =>
+    val boom = LazyModule(new BoomTile(tp, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
+
+    connectMasterPortsToSBus(boom, crossing)
+    connectSlavePortsToCBus(boom, crossing)
+
+    def treeNode: RocketTileLogicalTreeNode = new RocketTileLogicalTreeNode(boom.rocketLogicalTree.getOMInterruptTargets)
+    LogicalModuleTree.add(logicalTreeNode, boom.rocketLogicalTree)
+
+    boom
+  }
+
+  // combine tiles and connect interrupts based on the order of harts
+  val boomAndRocketTiles = (rocketTiles ++ boomTiles).sortWith(_.tileParams.hartId < _.tileParams.hartId).map {
+    tile => {
+      connectInterrupts(tile, Some(debug), clintOpt, plicOpt)
+
+      tile
+    }
+  }
+
+  def coreMonitorBundles = (rocketTiles map { t => t.module.core.rocketImpl.coreMonitorBundle}).toList ++
+                             (boomTiles map { t => t.module.core.coreMonitorBundle}).toList
+}
+
+trait HasBoomAndRocketTilesModuleImp extends HasTilesModuleImp
+  with HasPeripheryDebugModuleImp
+{
+  val outer: HasBoomAndRocketTiles
+}
+
+class Subsystem(implicit p: Parameters) extends BaseSubsystem
+  with HasBoomAndRocketTiles
+{
+  val tiles = boomAndRocketTiles
+  override lazy val module = new SubsystemModuleImp(this)
+
+  def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
+}
+
+class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
+  with HasResetVectorWire
+  with HasBoomAndRocketTilesModuleImp
+{
+  tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
+    wire.hartid := i.U
+    wire.reset_vector := global_reset_vector
+  }
+
+  // create file with boom params
+  ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
+}

generators/utilities/src/main/scala/System.scala

@@ -0,0 +1,45 @@
+//******************************************************************************
+// Copyright (c) 2019 - 2019, The Regents of the University of California (Regents).
+// All Rights Reserved. See LICENSE and LICENSE.SiFive for license details.
+//------------------------------------------------------------------------------
+
+package utilities
+
+import chisel3._
+
+import freechips.rocketchip.config.{Parameters}
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.devices.tilelink._
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.util.{DontTouch}
+
+// ---------------------------------------------------------------------
+// Base system that uses the debug test module (dtm) to bringup the core
+// ---------------------------------------------------------------------
+
+/**
+ * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
+ */
+class System(implicit p: Parameters) extends Subsystem
+  with HasHierarchicalBusTopology
+  with HasAsyncExtInterrupts
+  with CanHaveMasterAXI4MemPort
+  with CanHaveMasterAXI4MMIOPort
+  with CanHaveSlaveAXI4Port
+  with HasPeripheryBootROM
+{
+  override lazy val module = new SystemModule(this)
+}
+
+/**
+ * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
+ */
+class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
+  with HasRTCModuleImp
+  with HasExtInterruptsModuleImp
+  with CanHaveMasterAXI4MemPortModuleImp
+  with CanHaveMasterAXI4MMIOPortModuleImp
+  with CanHaveSlaveAXI4PortModuleImp
+  with HasPeripheryBootROMModuleImp
+  with DontTouch

generators/utilities/src/main/scala/TestSuites.scala

@@ -1,4 +1,4 @@
-package example
+package utilities
 
 import scala.collection.mutable.{LinkedHashSet}
 
@@ -8,7 +8,7 @@ import freechips.rocketchip.config.{Parameters}
 import freechips.rocketchip.util.{GeneratorApp}
 import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite}
 
-import boom.system.{BoomTilesKey}
+import boom.common.{BoomTilesKey}
 
 /**
  * A set of pre-chosen regression tests