power straps fixes, sha3 w/ dco skeleton

vlsi/example.yml

@@ -45,7 +45,11 @@ par.generate_power_straps_options:
       - M7
       - M8
       - M9
-    track_width: 6
+    track_width: 14
+    track_width_M3: 7
+    track_width_M5: 24
+    track_width_M8: 6
+    track_width_M9: 6
     track_spacing: 0
     power_utilization: 0.05
     power_utilization_M8: 1.0
@@ -53,7 +57,7 @@ par.generate_power_straps_options:
 
 # Placement Constraints
 vlsi.inputs.placement_constraints:
-  - path: "Sha3Accel"
+  - path: "Sha3AccelwBB"
     type: "toplevel"
     x: 0
     y: 0
@@ -64,6 +68,13 @@ vlsi.inputs.placement_constraints:
       right: 0
       top: 0
       bottom: 0
+  - path: "Sha3AccelwBB/dco"
+    type: "hardmacro"
+    x: 400
+    y: 400
+    width: 32
+    height: 32
+    orientation: "r0"
 
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
@@ -72,6 +83,32 @@ vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["M5", "M7"], side: "bottom"}
 ]
 
+# Paths to extra libraries
+vlsi.technology.extra_libraries_meta: "append"
+vlsi.technology.extra_libraries:
+  - library:
+      nldm liberty file: "extra_libraries/dco/dco_SS.lib"
+      lef file: "extra_libraries/dco/dco.lef"
+      gds file: "extra_libraries/dco/dco.gds"
+      corner:
+        nmos: "slow"
+        pmos: "slow"
+        temperature: "100 C"
+      supplies:
+        VDD: "0.63 V"
+        GND: "0 V"
+  - library:
+      nldm liberty file: "extra_libraries/dco/dco_FF.lib"
+      lef file: "extra_libraries/dco/dco.lef"
+      gds file: "extra_libraries/dco/dco.gds"
+      corner:
+        nmos: "fast"
+        pmos: "fast"
+        temperature: "0 C"
+      supplies:
+        VDD: "0.77 V"
+        GND: "0 V"
+
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "sram_compiler"
 vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]