diff --git a/vlsi/Makefile b/vlsi/Makefile
index 6fcedd62..f4697a9b 100644
--- a/vlsi/Makefile
+++ b/vlsi/Makefile
@@ -33,7 +33,7 @@ HAMMER_EXEC        ?= ./example-vlsi
 # general rules
 #########################################################################################
 ALL_RTL = $(TOP_FILE) $(TOP_SMEMS_FILE) $(extra_v_includes)
-extra_v_includes = $(build_dir)/EICG_wrapper.v
+extra_v_includes = $(build_dir)/EICG_wrapper.v $(vlsi_dir)/example.v
 
 .PHONY: default verilog
 default: all
@@ -74,7 +74,7 @@ $(SRAM_CONF): $(SRAM_GENERATOR_CONF)
 # synthesis input configuration
 #########################################################################################
 SYN_CONF = $(OBJ_DIR)/inputs.yml
-GENERATED_CONFS = $(SYN_CONF) $(SRAM_CONF)
+GENERATED_CONFS = $(SYN_CONF) $(if $(filter $(tech_name), asap7), , $(SRAM_CONF))
 
 $(SYN_CONF): $(ALL_RTL) $(extra_v_includes) $(sim_top_blackboxes)
 	mkdir -p $(dir $@)
diff --git a/vlsi/README.md b/vlsi/README.md
index 7df19a12..12cb6fd9 100644
--- a/vlsi/README.md
+++ b/vlsi/README.md
@@ -7,22 +7,17 @@ If you are a UCB-affiliate, you may be able to acquire access to the tool & tech
 # Initial Setup Instructions (For all technologies)
 Run the `init-vlsi.sh` script to pull correct versions of hammer, hammer-TOOL\_VENDOR-plugins, and the hammer-TECH\_NAME-plugins. Note the included technology 'asap7' is already included and will not submodule a tech plugin.
 ```shell
-scripts/init-vlsi.sh TECH_NAME
+./scripts/init-vlsi.sh TECH_NAME
 ```
 
 An example of tool environment configuration for BWRC affiliates is given in `bwrc-env.yml`. Replace as necessary for your environment.
 
-Finally, set up all prerequisites for the build system:
-```shell
-make buildfile
-```
-
 # Example design
-In this example, you will be running a SHA-3 accelerator through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system:
+In this example, you will be running a SHA-3 accelerator with a dummy hard macro through the VLSI flow in the ASAP7 process. To elaborate the Sha3RocketConfig and set up all prerequisites for the build system:
 ```shell
 export MACROCOMPILER_MODE=' --mode synflops'
 export CONFIG=Sha3RocketConfig
-export TOP=Sha3Accel
+export TOP=Sha3AccelwBB
 make buildfile
 ```
 Note that because the ASAP7 process does not yet have a memory compiler, synflops are elaborated instead.
diff --git a/vlsi/example.v b/vlsi/example.v
new file mode 100644
index 00000000..bd0d3f9d
--- /dev/null
+++ b/vlsi/example.v
@@ -0,0 +1,154 @@
+// Extracted Sha3Accel w/ a blackbox (a dummy DCO) included inside
+
+module Sha3AccelwBB( // @[:example.TestHarness.Sha3RocketConfig.fir@135905.2]
+  input         clock, // @[:example.TestHarness.Sha3RocketConfig.fir@135906.4]
+  input         reset, // @[:example.TestHarness.Sha3RocketConfig.fir@135907.4]
+  output        io_cmd_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input         io_cmd_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input  [6:0]  io_cmd_bits_inst_funct, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input  [63:0] io_cmd_bits_rs1, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input  [63:0] io_cmd_bits_rs2, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input         io_mem_req_ready, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  output        io_mem_req_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  output [39:0] io_mem_req_bits_addr, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  output [7:0]  io_mem_req_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  output [4:0]  io_mem_req_bits_cmd, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  output [63:0] io_mem_req_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input         io_mem_resp_valid, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input  [7:0]  io_mem_resp_bits_tag, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input  [63:0] io_mem_resp_bits_data, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  output        io_busy, // @[:example.TestHarness.Sha3RocketConfig.fir@135909.4]
+  input  [13:0] col_sel_b,
+  input  [15:0] row_sel_b,
+  input  [7:0]  code_regulator,
+  input         dither,
+  input         sleep_b,
+  output        dco_clock
+);
+  wire clock; // from dummy DCO
+  wire  ctrl_clock; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_reset; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_rocc_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_rocc_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [1:0] ctrl_io_rocc_funct; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [63:0] ctrl_io_rocc_rs1; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [63:0] ctrl_io_rocc_rs2; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_busy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_dmem_req_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_dmem_req_rdy; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [6:0] ctrl_io_dmem_req_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [31:0] ctrl_io_dmem_req_addr; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [4:0] ctrl_io_dmem_req_cmd; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_dmem_resp_val; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [6:0] ctrl_io_dmem_resp_tag; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [63:0] ctrl_io_dmem_resp_data; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [4:0] ctrl_io_round; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_absorb; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [4:0] ctrl_io_aindex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_init; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  ctrl_io_write; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [2:0] ctrl_io_windex; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire [63:0] ctrl_io_buffer_out; // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+  wire  dpath_clock; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire  dpath_reset; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire  dpath_io_absorb; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire  dpath_io_init; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire  dpath_io_write; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [4:0] dpath_io_round; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [4:0] dpath_io_aindex; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [63:0] dpath_io_message_in; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [63:0] dpath_io_hash_out_0; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [63:0] dpath_io_hash_out_1; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [63:0] dpath_io_hash_out_2; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [63:0] dpath_io_hash_out_3; // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+  wire [1:0] _T; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4]
+  wire [63:0] _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  wire [63:0] _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  wire [63:0] _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  CtrlModule ctrl ( // @[sha3.scala 61:20:example.TestHarness.Sha3RocketConfig.fir@135916.4]
+    .clock(ctrl_clock),
+    .reset(ctrl_reset),
+    .io_rocc_req_val(ctrl_io_rocc_req_val),
+    .io_rocc_req_rdy(ctrl_io_rocc_req_rdy),
+    .io_rocc_funct(ctrl_io_rocc_funct),
+    .io_rocc_rs1(ctrl_io_rocc_rs1),
+    .io_rocc_rs2(ctrl_io_rocc_rs2),
+    .io_busy(ctrl_io_busy),
+    .io_dmem_req_val(ctrl_io_dmem_req_val),
+    .io_dmem_req_rdy(ctrl_io_dmem_req_rdy),
+    .io_dmem_req_tag(ctrl_io_dmem_req_tag),
+    .io_dmem_req_addr(ctrl_io_dmem_req_addr),
+    .io_dmem_req_cmd(ctrl_io_dmem_req_cmd),
+    .io_dmem_resp_val(ctrl_io_dmem_resp_val),
+    .io_dmem_resp_tag(ctrl_io_dmem_resp_tag),
+    .io_dmem_resp_data(ctrl_io_dmem_resp_data),
+    .io_round(ctrl_io_round),
+    .io_absorb(ctrl_io_absorb),
+    .io_aindex(ctrl_io_aindex),
+    .io_init(ctrl_io_init),
+    .io_write(ctrl_io_write),
+    .io_windex(ctrl_io_windex),
+    .io_buffer_out(ctrl_io_buffer_out)
+  );
+  DpathModule dpath ( // @[sha3.scala 82:21:example.TestHarness.Sha3RocketConfig.fir@135936.4]
+    .clock(dpath_clock),
+    .reset(dpath_reset),
+    .io_absorb(dpath_io_absorb),
+    .io_init(dpath_io_init),
+    .io_write(dpath_io_write),
+    .io_round(dpath_io_round),
+    .io_aindex(dpath_io_aindex),
+    .io_message_in(dpath_io_message_in),
+    .io_hash_out_0(dpath_io_hash_out_0),
+    .io_hash_out_1(dpath_io_hash_out_1),
+    .io_hash_out_2(dpath_io_hash_out_2),
+    .io_hash_out_3(dpath_io_hash_out_3)
+  );
+  ExampleDCO dco (
+    .col_sel_b(col_sel_b),
+    .row_sel_b(row_sel_b),
+    .code_regulator(code_regulator),
+    .dither(dither),
+    .sleep_b(sleep_b),
+    .clock(dco_clock)
+  );
+  assign _T = ctrl_io_windex[1:0]; // @[:example.TestHarness.Sha3RocketConfig.fir@135941.4]
+  assign _GEN_0 = dpath_io_hash_out_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  assign _GEN_1 = 2'h1 == _T ? dpath_io_hash_out_1 : _GEN_0; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  assign _GEN_2 = 2'h2 == _T ? dpath_io_hash_out_2 : _GEN_1; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  assign io_cmd_ready = ctrl_io_rocc_req_rdy; // @[sha3.scala 64:16:example.TestHarness.Sha3RocketConfig.fir@135921.4]
+  assign io_mem_req_valid = ctrl_io_dmem_req_val; // @[sha3.scala 71:20:example.TestHarness.Sha3RocketConfig.fir@135927.4]
+  assign io_mem_req_bits_addr = {{8'd0}, ctrl_io_dmem_req_addr}; // @[sha3.scala 74:24:example.TestHarness.Sha3RocketConfig.fir@135930.4]
+  assign io_mem_req_bits_tag = {{1'd0}, ctrl_io_dmem_req_tag}; // @[sha3.scala 73:23:example.TestHarness.Sha3RocketConfig.fir@135929.4]
+  assign io_mem_req_bits_cmd = ctrl_io_dmem_req_cmd; // @[sha3.scala 75:23:example.TestHarness.Sha3RocketConfig.fir@135931.4]
+  assign io_mem_req_bits_data = 2'h3 == _T ? dpath_io_hash_out_3 : _GEN_2; // @[sha3.scala 85:24:example.TestHarness.Sha3RocketConfig.fir@135942.4]
+  assign io_busy = ctrl_io_busy; // @[sha3.scala 69:11:example.TestHarness.Sha3RocketConfig.fir@135926.4]
+  assign ctrl_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135918.4]
+  assign ctrl_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135919.4]
+  assign ctrl_io_rocc_req_val = io_cmd_valid; // @[sha3.scala 63:26:example.TestHarness.Sha3RocketConfig.fir@135920.4]
+  assign ctrl_io_rocc_funct = io_cmd_bits_inst_funct[1:0]; // @[sha3.scala 65:26:example.TestHarness.Sha3RocketConfig.fir@135922.4]
+  assign ctrl_io_rocc_rs1 = io_cmd_bits_rs1; // @[sha3.scala 66:26:example.TestHarness.Sha3RocketConfig.fir@135923.4]
+  assign ctrl_io_rocc_rs2 = io_cmd_bits_rs2; // @[sha3.scala 67:26:example.TestHarness.Sha3RocketConfig.fir@135924.4]
+  assign ctrl_io_dmem_req_rdy = io_mem_req_ready; // @[sha3.scala 72:26:example.TestHarness.Sha3RocketConfig.fir@135928.4]
+  assign ctrl_io_dmem_resp_val = io_mem_resp_valid; // @[sha3.scala 78:26:example.TestHarness.Sha3RocketConfig.fir@135933.4]
+  assign ctrl_io_dmem_resp_tag = io_mem_resp_bits_tag[6:0]; // @[sha3.scala 79:26:example.TestHarness.Sha3RocketConfig.fir@135934.4]
+  assign ctrl_io_dmem_resp_data = io_mem_resp_bits_data; // @[sha3.scala 80:26:example.TestHarness.Sha3RocketConfig.fir@135935.4]
+  assign dpath_clock = clock; // @[:example.TestHarness.Sha3RocketConfig.fir@135938.4]
+  assign dpath_reset = reset; // @[:example.TestHarness.Sha3RocketConfig.fir@135939.4]
+  assign dpath_io_absorb = ctrl_io_absorb; // @[sha3.scala 88:19:example.TestHarness.Sha3RocketConfig.fir@135943.4]
+  assign dpath_io_init = ctrl_io_init; // @[sha3.scala 89:17:example.TestHarness.Sha3RocketConfig.fir@135944.4]
+  assign dpath_io_write = ctrl_io_write; // @[sha3.scala 90:18:example.TestHarness.Sha3RocketConfig.fir@135945.4]
+  assign dpath_io_round = ctrl_io_round; // @[sha3.scala 91:18:example.TestHarness.Sha3RocketConfig.fir@135946.4]
+  assign dpath_io_aindex = ctrl_io_aindex; // @[sha3.scala 93:19:example.TestHarness.Sha3RocketConfig.fir@135948.4]
+  assign dpath_io_message_in = ctrl_io_buffer_out; // @[sha3.scala 84:23:example.TestHarness.Sha3RocketConfig.fir@135940.4]
+endmodule
+
+module ExampleDCO (
+  input  [13:0] col_sel_b,
+  input  [15:0] row_sel_b,
+  input  [7:0]  code_regulator,
+  input         dither,
+  input         sleep_b,
+  output        clock
+);
+endmodule
diff --git a/vlsi/example.yml b/vlsi/example.yml
index ffa7e732..8616fa33 100644
--- a/vlsi/example.yml
+++ b/vlsi/example.yml
@@ -45,7 +45,11 @@ par.generate_power_straps_options:
       - M7
       - M8
       - M9
-    track_width: 6
+    track_width: 14
+    track_width_M3: 7
+    track_width_M5: 24
+    track_width_M8: 6
+    track_width_M9: 6
     track_spacing: 0
     power_utilization: 0.05
     power_utilization_M8: 1.0
@@ -53,7 +57,7 @@ par.generate_power_straps_options:
 
 # Placement Constraints
 vlsi.inputs.placement_constraints:
-  - path: "Sha3Accel"
+  - path: "Sha3AccelwBB"
     type: "toplevel"
     x: 0
     y: 0
@@ -64,6 +68,13 @@ vlsi.inputs.placement_constraints:
       right: 0
       top: 0
       bottom: 0
+  - path: "Sha3AccelwBB/dco"
+    type: "hardmacro"
+    x: 400
+    y: 400
+    width: 32
+    height: 32
+    orientation: "r0"
 
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
@@ -72,6 +83,32 @@ vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["M5", "M7"], side: "bottom"}
 ]
 
+# Paths to extra libraries
+vlsi.technology.extra_libraries_meta: "append"
+vlsi.technology.extra_libraries:
+  - library:
+      nldm liberty file: "extra_libraries/dco/dco_SS.lib"
+      lef file: "extra_libraries/dco/dco.lef"
+      gds file: "extra_libraries/dco/dco.gds"
+      corner:
+        nmos: "slow"
+        pmos: "slow"
+        temperature: "100 C"
+      supplies:
+        VDD: "0.63 V"
+        GND: "0 V"
+  - library:
+      nldm liberty file: "extra_libraries/dco/dco_FF.lib"
+      lef file: "extra_libraries/dco/dco.lef"
+      gds file: "extra_libraries/dco/dco.gds"
+      corner:
+        nmos: "fast"
+        pmos: "fast"
+        temperature: "0 C"
+      supplies:
+        VDD: "0.77 V"
+        GND: "0 V"
+
 # SRAM Compiler compiler options
 vlsi.core.sram_generator_tool: "sram_compiler"
 vlsi.core.sram_generator_tool_path: ["SPECIFY LOCATION OF SRAM GENERATOR IN TECH PLUGIN"]
diff --git a/vlsi/extra_libraries/dco/dco.gds b/vlsi/extra_libraries/dco/dco.gds
new file mode 100644
index 00000000..e5cb24a3
Binary files /dev/null and b/vlsi/extra_libraries/dco/dco.gds differ
diff --git a/vlsi/extra_libraries/dco/dco.lef b/vlsi/extra_libraries/dco/dco.lef
new file mode 100644
index 00000000..24a878f9
--- /dev/null
+++ b/vlsi/extra_libraries/dco/dco.lef
@@ -0,0 +1,376 @@
+VERSION 5.6 ;
+BUSBITCHARS "[]" ;
+DIVIDERCHAR "/" ;
+
+MACRO dco-layout
+  CLASS CORE ;
+  ORIGIN 0 0 ;
+  FOREIGN dco-layout 0 0 ;
+  SIZE 32 BY 32 ;
+  SYMMETRY X Y ;
+  SITE CoreSite ;
+  PIN VDD
+    DIRECTION INOUT ;
+    USE POWER ;
+    PORT
+      LAYER M9 ;
+        RECT 8.42 31 8.58 32 ;
+    END
+  END VDD
+  PIN VSS
+    DIRECTION INOUT ;
+    USE GROUND ;
+    PORT
+      LAYER M9 ;
+        RECT 23.432 31 23.592 32 ;
+    END
+  END VSS
+  PIN col_sel_b[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 30.202 1.00 30.298 ;
+    END
+  END col_sel_b[13]
+  PIN col_sel_b[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 28.702 1.00 28.798 ;
+    END
+  END col_sel_b[11]
+  PIN col_sel_b[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 24.202 1.00 24.298 ;
+    END
+  END col_sel_b[5]
+  PIN col_sel_b[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 29.452 1.00 29.548 ;
+    END
+  END col_sel_b[12]
+  PIN col_sel_b[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 27.952 1.00 28.048 ;
+    END
+  END col_sel_b[10]
+  PIN col_sel_b[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 27.202 1.00 27.298 ;
+    END
+  END col_sel_b[9]
+  PIN col_sel_b[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 26.452 1.00 26.548 ;
+    END
+  END col_sel_b[8]
+  PIN col_sel_b[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 25.702 1.00 25.798 ;
+    END
+  END col_sel_b[7]
+  PIN col_sel_b[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 24.952 1.00 25.048 ;
+    END
+  END col_sel_b[6]
+  PIN col_sel_b[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 23.452 1.00 23.548 ;
+    END
+  END col_sel_b[4]
+  PIN col_sel_b[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 22.702 1.00 22.798 ;
+    END
+  END col_sel_b[3]
+  PIN col_sel_b[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 21.952 1.00 22.048 ;
+    END
+  END col_sel_b[2]
+  PIN col_sel_b[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 21.202 1.00 21.298 ;
+    END
+  END col_sel_b[1]
+  PIN col_sel_b[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 20.452 1.00 20.548 ;
+    END
+  END col_sel_b[0]
+  PIN row_sel_b[14]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 18.952 1.00 19.048 ;
+    END
+  END row_sel_b[14]
+  PIN row_sel_b[13]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 18.202 1.00 18.298 ;
+    END
+  END row_sel_b[13]
+  PIN row_sel_b[12]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 17.452 1.00 17.548 ;
+    END
+  END row_sel_b[12]
+  PIN row_sel_b[11]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 16.702 1.00 16.798 ;
+    END
+  END row_sel_b[11]
+  PIN row_sel_b[10]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 15.952 1.00 16.048 ;
+    END
+  END row_sel_b[10]
+  PIN row_sel_b[9]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 15.202 1.00 15.298 ;
+    END
+  END row_sel_b[9]
+  PIN row_sel_b[8]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 14.452 1.00 14.548 ;
+    END
+  END row_sel_b[8]
+  PIN row_sel_b[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 13.702 1.00 13.798 ;
+    END
+  END row_sel_b[7]
+  PIN row_sel_b[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 12.952 1.00 13.048 ;
+    END
+  END row_sel_b[6]
+  PIN row_sel_b[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 12.202 1.00 12.298 ;
+    END
+  END row_sel_b[5]
+  PIN row_sel_b[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 11.452 1.00 11.548 ;
+    END
+  END row_sel_b[4]
+  PIN row_sel_b[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 10.702 1.00 10.798 ;
+    END
+  END row_sel_b[3]
+  PIN row_sel_b[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 9.952 1.00 10.048 ;
+    END
+  END row_sel_b[2]
+  PIN row_sel_b[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 9.202 1.00 9.298 ;
+    END
+  END row_sel_b[1]
+  PIN row_sel_b[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 8.452 1.00 8.548 ;
+    END
+  END row_sel_b[0]
+  PIN code_regulator[7]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 7.702 1.00 7.798 ;
+    END
+  END code_regulator[7]
+  PIN code_regulator[6]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 6.952 1.00 7.048 ;
+    END
+  END code_regulator[6]
+  PIN code_regulator[5]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 6.202 1.00 6.298 ;
+    END
+  END code_regulator[5]
+  PIN code_regulator[4]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 5.452 1.00 5.548 ;
+    END
+  END code_regulator[4]
+  PIN code_regulator[3]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 4.702 1.00 4.798 ;
+    END
+  END code_regulator[3]
+  PIN code_regulator[2]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 3.952 1.00 4.048 ;
+    END
+  END code_regulator[2]
+  PIN code_regulator[1]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 3.202 1.00 3.298 ;
+    END
+  END code_regulator[1]
+  PIN code_regulator[0]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 2.452 1.00 2.548 ;
+    END
+  END code_regulator[0]
+  PIN row_sel_b[15]
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0.002 19.702 1.002 19.798 ;
+    END
+  END row_sel_b[15]
+  PIN dither
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 0 1.702 1.00 1.798 ;
+    END
+  END dither
+  PIN sleep_b
+    DIRECTION INPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M5 ;
+        RECT 2.466 0 2.562 1 ;
+    END
+  END sleep_b
+  PIN clock
+    DIRECTION OUTPUT ;
+    USE SIGNAL ;
+    PORT
+      LAYER M4 ;
+        RECT 31 17.452 32 17.548 ;
+    END
+  END clock
+  OBS
+    LAYER M1 ;
+      RECT 1 1 31 31 ;
+    LAYER M2 ;
+      RECT 1 1 31 31 ;
+    LAYER M3 ;
+      RECT 1 1 31 31 ;
+    LAYER M4 ;
+      RECT 1 1 31 31 ;
+    LAYER M5 ;
+      RECT 1 1 31 31 ;
+    LAYER M6 ;
+      RECT 1 1 31 31 ;
+    LAYER M7 ;
+      RECT 1 1 31 31 ;
+    LAYER M8 ;
+      RECT 1 1 31 31 ;
+  END
+END dco-layout
+
+END LIBRARY
diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins
index a0741281..a9762c34 160000
--- a/vlsi/hammer-cadence-plugins
+++ b/vlsi/hammer-cadence-plugins
@@ -1 +1 @@
-Subproject commit a07412814b878c67d79f7aada598848bcb4c197c
+Subproject commit a9762c344ea247eb2174e720bf8507daf3226933