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Bump rocket-chip

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This commit is contained in:
Jerry Zhao
2023-10-18 00:27:05 -07:00
parent e8aa68c65c
commit 686d9a5f44
2 changed files with 10 additions and 2 deletions
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2
generators/rocket-chip

Submodule generators/rocket-chip updated: e0ea90344e...d48b45da56

10
generators/tracegen/src/main/scala/System.scala
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@@ -11,14 +11,22 @@ import boom.lsu.BoomTraceGenTile
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with InstantiatesHierarchicalElements with InstantiatesHierarchicalElements
with HasTileNotificationSinks with HasTileNotificationSinks
with HasTileInputConstants
with HasHierarchicalElementsRootContext
with HasHierarchicalElements
with CanHaveMasterAXI4MemPort { with CanHaveMasterAXI4MemPort {
def coreMonitorBundles = Nil def coreMonitorBundles = Nil
val tileStatusNodes = totalTiles.values.toSeq.collect { val tileStatusNodes = totalTiles.values.toSeq.collect {
case t: GroundTestTile => t.statusNode.makeSink() case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink() case t: BoomTraceGenTile => t.statusNode.makeSink()
} }
lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
lazy val clintOpt = None
lazy val debugOpt = None
lazy val plicOpt = None
override lazy val module = new TraceGenSystemModuleImp(this) override lazy val module = new TraceGenSystemModuleImp(this)
} }