Refactor tapeout for Chisel 3.4, Firrtl 1.4
- Remove clk package based on discussion with Colin - Annotations need to be refactored to using latest API - Generally that involves making annos generated by a anonymous ChiselAnnotation - The chisel annotations will use RunFirrtlTransform to queue up its associated transform - Chisel annotation provieds toFirrtl to generate Firrtl form of annotation - Usages of unapply on firrtl annotations cannot use generic unapply(target, transform, data) which has been eliminated - Have transforms use with DependencyAPIMigration to avoid deprecated `form`s - Added some 'see License comments - TechnologyLocation section of AddIOPadsSpec does not currently run because there is no content for it. - Added some tests for annotation serialization here
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@@ -3,24 +3,19 @@
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package barstools.tapeout.transforms.pads
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import firrtl._
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import firrtl.annotations._
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import firrtl.passes._
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import firrtl.ir._
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import barstools.tapeout.transforms._
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import scala.collection.mutable
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// Main Add IO Pad transform operates on low Firrtl
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class AddIOPadsTransform extends Transform with SeqTransformBased {
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override def inputForm: CircuitForm = LowForm
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override def outputForm: CircuitForm = LowForm
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class AddIOPadsTransform extends Transform with SeqTransformBased with DependencyAPIMigration {
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val transformList = new mutable.ArrayBuffer[Transform]
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def transforms: Seq[Transform] = transformList
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override def execute(state: CircuitState): CircuitState = {
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val collectedAnnos = HasPadAnnotation(getMyAnnotations(state))
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val collectedAnnos = HasPadAnnotation(state.annotations)
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collectedAnnos match {
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// Transform not used
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case None => state
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@@ -77,7 +77,12 @@ abstract class TopModule(
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// Annotate IO with side + pad name
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def annotatePad(sig: Element, side: PadSide = defaultPadSide, name: String = ""): Unit = if (usePads) {
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val anno = IOPadAnnotation(side.serialize, name)
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annotate(TargetIOPadAnnoC(sig, anno))
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annotate(new ChiselAnnotation with RunFirrtlTransform {
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override def toFirrtl: Annotation = {
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TargetIOPadAnnoF(sig.toTarget, anno)
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}
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def transformClass: Class[_ <: Transform] = classOf[AddIOPadsTransform]
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})
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}
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def annotatePad(sig: Aggregate, name: String): Unit = annotatePad(sig, side = defaultPadSide, name)
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def annotatePad(sig: Aggregate, side: PadSide): Unit = annotatePad(sig, side, name = "")
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@@ -86,7 +91,16 @@ abstract class TopModule(
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// There may be cases where pads were inserted elsewhere. If that's the case, allow certain IO to
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// not have pads auto added. Note that annotatePad and noPad are mutually exclusive!
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def noPad(sig: Element): Unit = if (usePads) annotate(TargetIOPadAnnoC(sig, NoIOPadAnnotation()))
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def noPad(sig: Element): Unit = {
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if (usePads) {
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annotate(new ChiselAnnotation with RunFirrtlTransform {
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override def toFirrtl: Annotation = {
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TargetIOPadAnnoF(sig.toTarget, NoIOPadAnnotation())
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}
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def transformClass: Class[_ <: Transform] = classOf[AddIOPadsTransform]
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})
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}
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}
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def noPad(sig: Aggregate): Unit = extractElements(sig) foreach { x => noPad(x) }
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// Since this is a super class, this should be the first thing that gets run
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@@ -1,3 +1,5 @@
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// See LICENSE for license details.
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package barstools.tapeout.transforms.pads
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import net.jcazevedo.moultingyaml._
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@@ -85,8 +87,9 @@ object FoundryPadsYaml extends DefaultYamlProtocol {
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implicit val _pad = yamlFormat6(FoundryPad)
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def parse(techDir: String): Seq[FoundryPad] = {
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val file = techDir + exampleResource
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if(techDir != "" && !(new java.io.File(file)).exists())
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throw new Exception("Technology directory must contain FoundryPads.yaml!")
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if(techDir != "" && !(new java.io.File(file)).exists()) {
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throw new Exception(s"Technology directory $techDir must contain FoundryPads.yaml!")
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}
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val out = (new YamlFileReader(exampleResource)).parse[FoundryPad](if (techDir == "") "" else file)
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val padNames = out.map(x => x.correctedName)
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require(padNames.distinct.length == padNames.length, "Pad names must be unique!")
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@@ -3,9 +3,6 @@
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package barstools.tapeout.transforms.pads
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import firrtl.annotations._
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import chisel3.experimental._
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import chisel3._
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import net.jcazevedo.moultingyaml._
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object PadAnnotationsYaml extends DefaultYamlProtocol {
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@@ -13,6 +10,17 @@ object PadAnnotationsYaml extends DefaultYamlProtocol {
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implicit val _noiopad = yamlFormat1(NoIOPadAnnotation)
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implicit val _supplyanno = yamlFormat5(SupplyAnnotation)
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implicit val _modulepadanno = yamlFormat4(ModulePadAnnotation)
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// Putting these serialize methods here seems to fix warnings about missing implicits for the toYaml
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def serialize(noIOPad: NoIOPadAnnotation): String = {
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noIOPad.toYaml.prettyPrint
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}
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def serialize(ioPadAnnotation: IOPadAnnotation): String = {
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ioPadAnnotation.toYaml.prettyPrint
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}
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def serialize(modulePadAnnotation: ModulePadAnnotation): String = {
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modulePadAnnotation.toYaml.prettyPrint
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}
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}
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abstract class FirrtlPadTransformAnnotation {
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@@ -25,14 +33,12 @@ abstract class IOAnnotation {
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}
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case class IOPadAnnotation(padSide: String, padName: String) extends IOAnnotation {
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import PadAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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def serialize: String = PadAnnotationsYaml.serialize(this)
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def getPadSide: PadSide = HasPadAnnotation.getSide(padSide)
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}
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case class NoIOPadAnnotation(noPad: String = "") extends IOAnnotation {
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import PadAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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def serialize: String = PadAnnotationsYaml.serialize(this)
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def field: String = "noPad:"
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}
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@@ -44,12 +50,6 @@ case class TargetIOPadAnnoF(target: ComponentName, anno: IOAnnotation)
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def targetName: String = target.name
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}
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//TODO: PORT-1.4: Remove commented code
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// Chisel version
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//case class TargetIOPadAnnoC(target: Element, anno: IOAnnotation) extends ChiselAnnotation {
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// def toFirrtl = TargetIOPadAnnoF(target.toNamed, anno)
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//}
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// A bunch of supply pads (designated by name, # on each chip side) can be associated with the top module
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case class SupplyAnnotation(
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padName: String,
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@@ -64,9 +64,9 @@ case class ModulePadAnnotation(
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coreWidth: Int = 0,
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coreHeight: Int = 0,
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supplyAnnos: Seq[SupplyAnnotation] = Seq.empty) {
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import PadAnnotationsYaml._
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def serialize: String = this.toYaml.prettyPrint
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val supplyPadNames = supplyAnnos.map(_.padName)
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def serialize: String = PadAnnotationsYaml.serialize(this)
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def supplyPadNames: Seq[String] = supplyAnnos.map(_.padName)
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require(supplyPadNames.distinct.length == supplyPadNames.length, "Supply pads should only be specified once!")
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def getDefaultPadSide: PadSide = HasPadAnnotation.getSide(defaultPadSide)
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}
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@@ -91,7 +91,6 @@ case class CollectedAnnos(
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}
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object HasPadAnnotation {
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import PadAnnotationsYaml._
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def getSide(a: String): PadSide = a match {
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case i if i == Left.serialize => Left
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@@ -115,26 +114,13 @@ object HasPadAnnotation {
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// case _ => None
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// }
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//scalastyle:off cyclomatic.complexity
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def unapply(a: Annotation): Option[FirrtlPadTransformAnnotation] = a match {
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case hasTransform: RunFirrtlTransform if hasTransform.transformClass == classOf[AddIOPadsTransform] =>
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hasTransform match {
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case hasTarget: SingleTargetAnnotation[_] =>
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hasTarget.target match {
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case m: ModuleName =>
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Some(TargetModulePadAnnoF(m, s.parseYaml.convertTo[ModulePadAnnotation]))
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hasTarget match {
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case _ => None
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}
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}
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case _ => None
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}
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def apply(annos: Seq[Annotation]): Option[CollectedAnnos] = {
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// Get all pad-related annotations (config files, pad sides, pad names, etc.)
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val padAnnos = annos.map(x => unapply(x)).flatten
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val padAnnos = annos.flatMap {
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case a: TargetModulePadAnnoF => Some(a)
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case a: TargetIOPadAnnoF => Some(a)
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case _ => None
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}
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val targets = padAnnos.map(x => x.targetName)
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require(targets.distinct.length == targets.length, "Only 1 pad related annotation is allowed per component/module")
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if (padAnnos.length == 0) {
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