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Update WU architecture integration

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This commit is contained in:
abnerhexu
2026-05-25 19:26:23 +08:00
parent ec349a854f
commit 5ce98e1491
3 changed files with 11 additions and 10 deletions
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3
generators/chipyard/src/main/scala/config/RadianceConfigs.scala
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@@ -88,11 +88,12 @@ class Radiance4CFP16ClusterConfig extends Config(
class RadianceBlackwellClusterConfig extends Config(
new radiance.subsystem.WithRadianceGemmini(location = InCluster(0), dim = 16, accSizeInKB = 32, tileSize = (8, 4, 8), dataType = RadianceGemminiDataType.FP16) ++
new radiance.subsystem.WithRadianceCores(4, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, tensorCoreBlackwell = true, startupAddress = BigInt("80000000", 16), useVxCache = false) ++
new radiance.subsystem.WithRadianceCores(1, location = InCluster(0), tensorCoreFP16 = true, tensorCoreDecoupled = false, tensorCoreBlackwell = true, numTensorWarps = 2, startupAddress = BigInt("80000000", 16), useVxCache = false) ++
new radiance.subsystem.WithRadianceSharedMem(address = x"ff000000", size = 128 << 10, numBanks = 4, numWords = 8) ++
new radiance.subsystem.WithCoalescer(nNewSrcIds = 16) ++
new radiance.subsystem.WithVortexL1Banks(nBanks = 8) ++
new radiance.subsystem.WithRadianceCluster(0) ++
new radiance.subsystem.WithSimtConfig(nWarps = 4, nCoreLanes = 4, nMemLanes = 4, nSrcIds = 32) ++
new RadianceBaseConfig)
class RadianceClusterConfig extends Config(

2
generators/radiance

Submodule generators/radiance updated: 5112f3665a...87a4bbc757

16
sims/verilator/Makefile
View File

@@ -104,8 +104,9 @@ get_waveform_flag = +vcdfile=$(1).$(if $(filter $(USE_FST),0),vcd,fst)
#----------------------------------------------------------------------------------------
# we initially had --noassert for performance, but several modules use
# assertions, including dramsim, so we enable --assert by default
VERILATOR_OUTPUT_SPLIT ?= 10000
VERILATOR_OUTPUT_SPLIT_CFUNCS ?= 100
VERILATOR_OUTPUT_SPLIT ?= 2000
VERILATOR_OUTPUT_SPLIT_CFUNCS ?= 20
VERILATOR_OUTPUT_GROUPS ?= 0
VERILATOR_OPT_FLAGS ?= \
-O0 \
@@ -169,6 +170,7 @@ VERILATOR_NONCC_OPTS = \
VERILATOR_CXXFLAGS = \
$(SIM_CXXFLAGS) \
$(RUNTIME_PROFILING_CFLAGS) \
-O0 \
-fno-inline \
-DVERILATOR
@@ -199,25 +201,23 @@ model_mk_debug = $(model_dir_debug)/V$(TB).mk
# build makefile fragment that builds the verilator sim rules
#########################################################################################
$(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir)
mkdir -p $(model_dir)
$(VERILATOR) -j 36 $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
$(VERILATOR) -j $(VERILATOR_MAKE_JOBS) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim) -Mdir $(model_dir)
touch $@
$(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
rm -rf $(model_dir_debug)
mkdir -p $(model_dir_debug)
$(VERILATOR) -j 36 $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
$(VERILATOR) -j $(VERILATOR_MAKE_JOBS) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug)
touch $@
#########################################################################################
# invoke make to make verilator sim rules
#########################################################################################
$(sim): $(model_mk) $(dramsim_lib)
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O0 OPT_SLOW=-O0 OPT_GLOBAL=-O0 -C $(model_dir) -f V$(TB).mk
$(sim_debug): $(model_mk_debug) $(dramsim_lib)
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
$(MAKE) -j $(VERILATOR_MAKE_JOBS) VM_PARALLEL_BUILDS=1 OPT_FAST=-O0 OPT_SLOW=-O0 OPT_GLOBAL=-O0 -C $(model_dir_debug) -f V$(TB).mk
#########################################################################################
# create a verilator vpd rule